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Which wire or reg creates combination loop?

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Kuldeepluvani

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[DRC 23-20] Rule violation (LUTLP-1) Combinatorial Loop - 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. To allow bitstream creation for designs with combinatorial logic loops (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks LUTLP-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. an_OBUF[3]_inst_i_1.

I can post code if needed.
 

I've actually never tried to synthesize a design with an intentional combinatorial loop. Most likely you should look at the design and remove the loop. The loop occurs when signal "a" uses signal "b", while signal "b" also uses signal "a".

It sounds like the logic to generate "an_OCUF[3]_inst_i_1", probably an output called "an(3)" in your code, uses itself in the logic to generate itself. There is only 1 affected LUT, so the problem is probably small.

(a 1's complement adder is the only practical example I know for an intentional combinatorial loop. It can be implemented without the combinatorial loop as well.)
 

Combinational Loop is not allowed basically even you can see non-timing simulation result as correct one. It will be a problem on timing state. Post the code and your idea about it, then guys here can help to comment if any.
 

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