jagansai
Newbie level 2
can you tell the diff between this two assignments
Code VHDL - [expand] 1 2 3 if( rising_edge(clk))then d_in(width-1 downto 0)<= d_out(width-1 downto 0); end if;
Code VHDL - [expand] 1 2 3 4 5 if(rising_edge(clk)) then for i in 0 to width-1 loop d_in(i) <= d_out; end loop; end if;