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Distinguishing UDP, NBNS, LLMNR packets

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Hi Everebody,
I have problem to distinguish packet received on FPGA from PC. when I send packets from FPGA to PC, I receive correct packets but some time it also consists the packets from its higher protocols NBNS and LLMNR. The one way I can assume by putting some preamble(lets say FFFFFFFF) as a trigger with every sent packet from PC. I would like to know is there any way to trigger the reception that contain only sent UDP packets and not packets from NBNS, LLMNR, etc. without using preamble?

Regards
 

So you're sending packets from a PC to an FPGA and are getting packets other than UDP?

You must not be parsing the headers correctly. What does your header parsing logic do? Are you ignoring some of the header fields?

Is it valid to assume you are using an Ethernet MAC core provided by the FPGA vendor and not some custom core?
 

I got right UDP Packet but also the packets from NBNS, LLMNR. TO extract the payload, I compare the MAC address of PC and FPGA and UDP Protocol field of IP which is 17 (i.e. 11h) to start the payload. I read the payload length from UDP field and decrease it by 1 until it reaches the end to stop.
I am using Ethernet MAC Core.
 

Didn't have a chance to check the protocol formats until now, but what you are likely missing is the check for UDP port 137 for the NBNS and UDP port 5355 for LLMNR. Add those two ports to your packet dropping filter and you won't see them forwarded, there may be other types of UDP traffic you may want to also drop, so some sort of programmable packet dropping filter might be useful.
 
You should be filtering out or forwarding any packet that isn't useful. Filtering based on destination MAC, ethertype, IP version, IP IHL, IP fragment, IP protocol (udp), destination IP, and UDP destination port.
 

Is it allowed to check only some of registers coming from bit slicing with IF statements in verilog as below?

Code Verilog - [expand]
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localparam data_width = 4;
localparam shift_leng = 84;
reg [6:0] i = 0;
reg [data_width*shift_leng-1:0]  shift_reg; 
 
 
always @ (posedge test_250_mhz) 
begin
  shift_reg[data_width-1:0] <= ENET0_RX_DATA;
      for (i=1;i<shift_leng;i=i+1) 
          begin
             shift_reg[data_width*i +:data_width] <= shift_reg[data_width*(i-1) +:data_width];
          end
          
            
// Check MAC, UDP Protocol, Destination IP, UDP Port before starting payload
    if ((shift_reg[83:60] == 96'h0070DEFFF8010EBD556DF8F5) && (shift_reg[37:36] == 8'h11) && (shift_reg[23:16] == 32'ha0000010) && (shift_reg[11:8] == 16'h7107))
    begin
            trigger <= 1;
                        payload_length <=  shift_reg[7:4];  // Extract payload_length to stop payload 
          end
       
 end


I am asking because I couldn't observe trigger in signal tap ii.
 
Last edited:

All your widths are messed up:

Code Verilog - [expand]
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(shift_reg[83:60] == 96'h0070DEFFF8010EBD556DF8F5) // this is 24-bits compared to 96-bits
 && (shift_reg[37:36] == 8'h11) // 2-bits compared to 8-bits
 && (shift_reg[23:16] == 32'ha0000010) // 8-bits compared to 32-bits
 && (shift_reg[11:8] == 16'h7107) // 4-bits compared to 16-bits

Of course you don't get a trigger as you aren't comparing the right stuff.

You also might get false indications as there is nothing here to only compare the headers, In this case you can also potentially find matches in the payload if you're unlucky.
 
Hi,
I would like to know about a concept of executing multiple statements inside IF condition:
Code Verilog - [expand]
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always @ (clk)
begin
  count <= count + 1;
    if (count == 5)
       begin
            set <= 1; // Here can I execute multiple statement or not? Because count == 5 will be only one time(only   
                          // one clock cycle and to execute 3 statements like below takes 3 clock cycles) true.           
                         //Multiple statement mean:
                       //Set<= 1;
                       // other_value <= 1;
                       // another_value <= 2;   // etc.
       end
 
end
 

You can assign multiple signals in a begin-end block, in that example they would all get assigned on the clock edge when count is equal to 5.
 
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