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[SOLVED] Why don't Synplify Pro E-2010 generate mapped VHDL netlist?

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Sumathigokul

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Hi all,
I am using Libero IDE v9.1 (one year free version) which supports Synplify Pro E-2010 as synthesis tool. Synplify Pro has option to generate post-synthesis mapped VHDL netlist . Though i enabled optional output file check boxes (present in implementation results) to generate the corresponding VHDL netlist, it is not generating it. But, sometimes it do generate. So i could not figure out under which circumstances alone tool generates and when it is not???

Thank you.
 

amit.kumar11 said:
Hi,

It might be licence issue. Since you are using trail version.
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Hi all,

Problem is solved.
There is also an option in Libero IDE project settings->flow->generate HDL netlist after synthesis. This option should also be enabled itseems. Now it is generating mapped HDL file.


Thank you.
 

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