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Which of these VHDL assignments are correct?

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vishal_sonam

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-- signal declaration:
type T_Bit is integer;
signal A : T_Bit;
signal B : bit;
signal C : bit_vector(3 downto 0);
-- signal assignments:
A <= B;
B <= C(3);
B <= C(2);
 

Come on now. One homework question you got for free. Trying to get three is pushing your luck. :p
 
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