[SOLVED] problem with nonblocking assignment

dipin · Sep 26, 2014

hi,

Code:

    .............................      
       end else if(!o_complete) begin
            
                temp_in_data   = temp_in_data << 2;
             
               if(count > 0) begin
              
                   substraction  = temp_in_data[15:8] - temp_sub_result[7:0];
              
              
                    if(substraction >= 0) begin
                      
                      .......................

this is my code. i think in sequential ,we need to use nonblocking assignment... but if i put put nonblocking assignment then iam not getting the result.my idea is

the shifted data must used in substraction,
and after only completion of substraction ,i need to check weather it is + or _ve and do the rest . so if i do like this is it synthesizable in fpga??

if it is not possible ,,any other methode to do nonblocking assignment instead of blocking assignment?

thanks and regards

ads-ee · Sep 26, 2014

dipin said:
hi,

Code:

............................. end else if(!o_complete) begin temp_in_data = temp_in_data << 2; if(count > 0) begin substraction = temp_in_data[15:8] - temp_sub_result[7:0]; if(substraction >= 0) begin .......................

this is my code. i think in sequential ,we need to use nonblocking assignment... but if i put put nonblocking assignment then iam not getting the result.

Because you aren't "think in sequential". Your code is written like an imperative program.

my idea is the shifted data must used in substraction, and after only completion of substraction ,i need to check weather it is + or _ve and do the rest . so if i do like this is it synthesizable in fpga??

Not if it is a sequential (@ (posedge clk)) clocked block.

if it is not possible ,,any other methode to do nonblocking assignment instead of blocking assignment?

Your problem doesn't lay with the blocking/non-blocking it's due to your lack of understanding what hardware you are trying to describe.

If you don't know what your circuit looks like, where the registers and logic are, how the pipeline is structured, then there is likely no way you'll write HDL code that will represent hardware. Therefore you end up with something that looks like a cross between a software program meets Verilog.

Try drawing both a timing diagram and a detailed block diagram showing the processing pipeline, with each stage of registers and how the processing is accomplished. Once you've done the "design" then you can bang away on the keyboard turning the design into HDL code.

Regards

mrflibble · Sep 26, 2014

ads-ee said:
Try drawing both a timing diagram and a detailed block diagram showing the processing pipeline, with each stage of registers and how the processing is accomplished. Once you've done the "design" then you can bang away on the keyboard turning the design into HDL code.

Yup. Exactly this!

dipin · Sep 29, 2014

hi
thanks for the replay.iam a beginer. actually my problem isthis, with in a single clock cycle
i need to assign a value to a register and with in the same clock i need to assign that register to another register.

Code:

         a_out_data     <=  a_out_data << 1;                    
                 
         a_out_data[0]  <=  1'b1;
                      
         temp_sub_result[5:2]  <= a_out_data[3:0];

before this step i am doing some calculation using temp_sub_result..

thanks

FvM · Sep 29, 2014

It's not generally impossible to pass several steps of data manipulation in a single clock cycle. In this case, blocking assignments may be used in sequential logic. But you should consider that timing closure becomes difficult at higher clock speed. And probably more important for a beginner, the code looses it straightforward style.

Verilog rules require in any case, that a particular variable has to be used on the left-hand side of either non-blocking (the regular case) or blocking assignments, but never both. The variables with non blocking assignment can be seen as intermediate results, like substraction in your example. If timing closure can be still achieved, it's O.K. to use it this way.

- - - Updated - - -

I should add, ads-ee is right nevertheless, that blocking asssignments in sequential code involve an abstraction from hardware description and bring up the risk of writing inefficient Verilog code. The usual way of effective logic hardware design is to serialize calculations over several clock cycles with registers holding the intermediate results. In so far it's a useful restriction to write sequential code without any blocking assignments.

ads-ee · Sep 29, 2014

dipin said:
hi
thanks for the replay.iam a beginer. actually my problem isthis, with in a single clock cycle
i need to assign a value to a register and with in the same clock i need to assign that register to another register.

Code:

a_out_data <= a_out_data << 1; a_out_data[0] <= 1'b1; temp_sub_result[5:2] <= a_out_data[3:0];

before this step i am doing some calculation using temp_sub_result..

thanks

Then you need to use the concatenation operation instead of the << 1 (shift left by 1). (your software background is showing ;-) )

What you want is this:

Code Verilog - [expand]
1
2
3
4
5
6
7
a_out_data <= {a_out_data[2:0], 1'b1}; // This is a very hardware-ish way of looking at a shift operation
 
// this is equivalent to typing out
a_out_data[3] <= a_out_data[2];
a_out_data[2] <= a_out_data[1];
a_out_data[1] <= a_out_data[0];
a_out_data[0] <= 1'b1;

Regards

dipin · Sep 30, 2014

hi,

thank you all.
regards

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[SOLVED] problem with nonblocking assignment

dipin

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mrflibble

dipin

mrflibble

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dipin

dipin

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FvM

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dipin

ads-ee

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dipin

dipin

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