simple logic circuit related question

Hi friends,
I have been braking my head the entire day to solve this simple problem.

1) 1 digital input low/high (will be continuous say if its low then it can be low for days and vice versa)
2)output needs to be high for n seconds and should be low when the input changes.

if I need to do with a mcu I would have done in minutes but i need to do without mcu and at the cheapest cost. I have been trying mono stable, bi stable combinations and serveral other logics but still not solution. can anyone help me providing a simple solution.

the code for the mcu is as simple as below but I need to do it with a logic circuit please help.

void main()
{
int last_state = 0;
input = Read_Input();
if( last_state != input )
{
last_state = input;
Set_Output(1);
delay(1000);
Set_Output(0);
}
}

Design a sequential circuit that does the same as your C code.

You need a clock to count so you can make a counter that counts out time, use the output of the counter to know when to turn off the output. Enable the counter when you have a change in the input signal...You pretty much did all that in the C code. The hardware to do this is really simple. clocks, counters, compare, and flip-flops to hold enables, input, and output.

I get the impression that some of the universities these students attend must not be very good, I've seen way too many posts like this. Their curriculum seems to make them software engineers with no understanding of logic design. Isn't logic design required in software design?

Dear Sir,
I have already solved the problem of the timing part using 555 in mono stable mode. I can adjust my time delay as required and can trigger it . its working fine. solved this part [Set_Output(1);delay(1000);Set_Output(0);] (with 1 555, 2 capacitor, 1 resistor)

my problem is much simplified now and the issue i face now is as below

if(input_change)
{
555_timer_monostable_mode(trigger_pulse)
}

how to detect a input change?
how to convert that change in to a pulse for 555 trigger ?

You posted this to the wrong forum, this is a PLD/CPLD/FPGA forum. You never specified that you were building a circuit with 555, caps, resistors.

I do FPGA designs, so I don't know what ICs are available to perform that kind of check. I suppose you could use positive and negative edge triggered flops with the D input connected to VCC and the output q's OR'd together to generate the trigger_pulse and clear the FF when you see that the pulse has gone high after trigger_pulse was generated. You might need a delay line to make sure the trigger_pulse stays high long enough for the 555.