imbichie
Full Member level 6
Hi all,
Is it possible to define the `define under the `ifdef and `elsif in verilog for synthesis.
When I did the same, it is simulating well, but when I synthesized the code its saying that the deines under teh `ifdef or `elsif are undeclared.
example:
here the defined parameters a and b are showing as undeclared during synthesis...
Thanks in Advance
Is it possible to define the `define under the `ifdef and `elsif in verilog for synthesis.
When I did the same, it is simulating well, but when I synthesized the code its saying that the deines under teh `ifdef or `elsif are undeclared.
example:
Code:
`define X
`define Y
`define Z
`ifdef X
`define a 2
`define b 3
`elsif Y
`define a 1
`define b 1
`elsif Z
`define a 2
`define b 1
`endif
here the defined parameters a and b are showing as undeclared during synthesis...
Thanks in Advance