Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] [Help]How to simulate the jitter of the VCO output in HSPICE

Status
Not open for further replies.
A

alanbrooke

Guest
Can anyone tell me the method to simulate the jitter performance of the VCO use HSPICE,
Thank you very much!
 

u can find the way in "cmos:mixed-signal IC design"
 

Re: [Help]How to simulate the jitter of the VCO output in HS

use cscope to measure vco jitter
 

Re: [Help]How to simulate the jitter of the VCO output in HS

lots of tools you can use
cscope
sandwork
you can see the eye diagram to see it
i use sandwork it is great
 

Re: [Help]How to simulate the jitter of the VCO output in HS

You can use .meas to measure n cycles VCO output.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top