amit.kn
Newbie level 2
Code VHDL - [expand] 1 [syntax=verilog]
Dear All,
I have a VHDL code in which i am using a std_logic_vector i.e
code:= std_logic_vector(255 downto 0);
I want to add all the bits and store into a vector of 8 downto 0.
Example:
if code = "010101......................0101", suppose we have 90 1's in code then ans should be 90 and should be stored in one more logic vector which is 8 downto 0.
Best Regards
Amit kumar