Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

VHDL Help. Weird issue with ADPLL

Status
Not open for further replies.
A

aobosong

Newbie level 5
Joined
Feb 27, 2011
Messages
9
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,352
Hello all.

This is my first VHDL design. I am running two separate ADPLLs, referenced to one reference.

The idea is that one ADPLL will generate a sine and cosine signal phase locked to the reference signal at the same frequency and the other PLL will generate waves at twice the frequency.

I synthesized the design and run it on Altium Nanoboard3000 (Xilinx Spartan 3A) with only one ADPLL running, both performed okay on their own.

However, when I combine them, the first one generates the correct frequency (same as the reference) but the second ADPLL generated a higher frequency than it should be :/


Code: 
--------------------------------------------------------------------------------
library ieee;
use     ieee.std_logic_1164.all;
use     ieee.numeric_std.all;

entity adplls is
    port
    (
    -- Basic Ports
        clock         : in  std_logic;                         -- 100MHz clock to control PLLs and DCOs
        adc_clock     : in  std_logic;                         -- the calcuations can only be done as fast the ADC is read into the device
        reset         : in  std_logic;                         -- reset channel
        ref_in           : in  std_logic;                      -- reference signal used in external reference set up
    -- DCO 1 output signals for debug
        dco1_sync_out  : out std_logic;                        -- DCO1's sync  output signal
        dco1_freq      : out std_logic_vector(29 downto 0);    -- DCO1 frequency tuning word
    -- DCO 2 output signals for debug
        dco2_sync_out  : out std_logic;                        -- DCO2's sync  output signal
        dco2_ndiv_out  : out std_logic;                        -- Divided down DCO2's sync signal (N divider output)
        dco2_freq      : out std_logic_vector(29 downto 0);    -- DCO2 frequency tuning word 
    );

End adplls;
------------------------------------------------------------

------------------------------------------------------------
architecture structure of adplls is
    
    signal this_pll1_freq_tune      : std_logic_vector(29 downto 0);  -- frequency tuning word generated by PLL1 
    signal this_pll2_freq_tune      : std_logic_vector(29 downto 0);  -- frequency tuning word generated by PLL2 
    
    signal this_sig_in         : std_logic_vector(17 downto 0);  -- signal input
    signal this_dco1_sin_out   : std_logic_vector(17 downto 0);  -- DCO1's sine signal output
    signal this_dco1_cos_out   : std_logic_vector(17 downto 0);  -- DCO1's cosine signal output
    signal this_dco1_sync_out  : std_logic;                      -- DCO1's sync out signal
    
    signal this_dco2_sin_out   : std_logic_vector(17 downto 0);  -- DCO2's sine signal output
    signal this_dco2_cos_out   : std_logic_vector(17 downto 0);  -- DCO2's cosine signal output
    signal this_dco2_sync_out  : std_logic;                      -- DCO2's sync out signal
    signal this_ndiv2_out      : std_logic;                      -- n divider output signal

    -- ADPLL
    component all_digital_pll                                 
        port
        (
            clock   : in  std_logic;                            -- ADPLL Clock, nominally 100 MHz
            reset   : in  std_logic;                            -- reset signal              
            ref_in  : in  std_logic;                            -- Reference signal input
            sync_in : in  std_logic;                            -- DCO sync signal input        
            freq    : out std_logic_vector(29 downto 0)         -- Frequency tuning word output
        );
    end component;

    -- DCO
    component digitally_controlled_oscillator                
        port
        (
            clock       : in  std_logic;                        -- DCO Clock, nominally 100 MHz
            reset       : in  std_logic;                        -- DCO reset signal
            freq_tune   : in  std_logic_vector(29 downto 0);    -- frequency tuning word input
            sync_output : out std_logic;                        -- sync output
            sigout_I    : out std_logic_vector(17 downto 0);    -- in phase signal output
            sigout_Q    : out std_logic_vector(17 downto 0);    -- quadrature signal output
        );
    end component;

    -- N Divider
    component n_divider
        generic
        (
            N : integer := 2
        );
        port
        (
            clock       : in    std_logic;                      -- input signal
            reset       : in    std_logic;                      -- reset signal
            div_clkout  : out   std_logic                       -- divided output
        );
    end component;



begin

    -------------------------------------
    -- Channel 1 Instantiations
    -------------------------------------
    -- All digital phase lock loop 
    CHAN1_ADPLL : all_digital_pll
    port map
    (
        clock   => clock,              -- 100 MHz clock
        reset   => reset,              -- global reset
        ref_in  => ref_in,             -- reference input signal
        sync_in => this_dco1_sync_out,      -- channel 1 is the fundamental channel, i.e. no n divider
                                            -- the dco sync output goes directly into the PLL
        freq    => this_pll1_freq_tune      -- output tuning word
    );

    -- Digitally Controlled Oscillators
    CHAN1_DCO : digitally_controlled_oscillator
    port map
    (
        clock       => clock,          -- 100 MHz clock
        reset       => reset,          -- global reset
        freq_tune   => this_pll1_freq_tune      , -- frequency tuning word input
        sync_output => this_dco1_sync_out,  -- DCO sync output
        sigout_I    => this_dco1_sin_out,   -- DCO sine signal output
        sigout_Q    => this_dco1_cos_out    -- DCO cosing signal output
    );


    -------------------------------------
    -- Channel 2 Instantiations
    -------------------------------------
    -- All digital phase lock loop
    CHAN2_ADPLL : all_digital_pll
    port map
    (
        clock   => clock,              -- 100 MHz clock
        reset   => reset,              -- global reset
        ref_in  => ref_in,             -- reference input signal
        sync_in => this_ndiv2_out,          -- channel 2 is the 2nd harmonics channel, need a n divider
        freq    => this_pll2_freq_tune      -- output tuning word
    );
    
    -- Digitally Controlled Oscillators
    CHAN2_DCO : digitally_controlled_oscillator
    port map
    (
        clock       => clock,          -- 100 MHz clock
        reset       => reset,          -- global reset
        freq_tune   => this_pll2_freq_tune, -- frequency tuning word input   
        sync_output => this_dco2_sync_out,  -- DCO sync output 
        sigout_I    => this_dco2_sin_out,   -- DCO sine signal output
        sigout_Q    => this_dco2_cos_out    -- DCO cosing signal output
    );
   
    -- Channel 2 N divider
    CHAN2_N_DIVIDER : n_divider
    generic map
    (
        N => 2  -- N = 2
    )
    port map
    (
        clock       =>  this_dco2_sync_out,
        reset       =>  reset,
        div_clkout  =>  this_ndiv2_out
    );

    dco1_sync_out   <=      this_dco1_sync_out;
    dco2_sync_out   <=      this_dco2_sync_out;
    dco2_ndiv_out   <=      this_ndiv2_out;
    dco1_freq       <=      this_dco1_freq_tune;
    dco2_freq       <=      this_dco2_freq_tune;


end structure;
------------------------------------------------------------
 

my guess is that it related to different place and route.
i.e when you par them seperately. the DCO and PLL were much closer, so propegation delay was low.
when you put togeter. then the faster one started to suffer from higher propgation delay so you got a drift.
 

Hi,

thanks for the reply. I thought it might be something like that too. Does this mean the code I put up there in my original post is okay and the problem lies within my sub modules?

Edit:

Instead of trying to get a reference signal from a signal generator. I generated a square waveform within the FPGA itself. The result is good, the DCOs and PLLs behave as expected.
Does the propagation delay from the IO pin really make this big difference? What should I do here?

This is a line from the UCF that I am using for the reference signal:

Code: 
Record=Constraint | TargetKind=Port       | TargetId=HB19               | FPGA_PINNUM=R10  | FPGA_SLEW = SLOW |  FPGA_IOSTANDARD =  LVCMOS33

The input signal is from an Agilent 33220A function generator SYNC port, measured to be a 3.3V square wave.
 
Last edited:

aobosong said:
Hi,

thanks for the reply. I thought it might be something like that too. Does this mean the code I put up there in my original post is okay and the problem lies within my sub modules?

Edit:

Instead of trying to get a reference signal from a signal generator. I generated a square waveform within the FPGA itself. The result is good, the DCOs and PLLs behave as expected.
Does the propagation delay from the IO pin really make this big difference? What should I do here?

This is a line from the UCF that I am using for the reference signal:

Code: 
Record=Constraint | TargetKind=Port       | TargetId=HB19               | FPGA_PINNUM=R10  | FPGA_SLEW = SLOW |  FPGA_IOSTANDARD =  LVCMOS33

The input signal is from an Agilent 33220A function generator SYNC port, measured to be a 3.3V square wave.
Click to expand...

are you buffering this signal mabee it can't drive 2 inputs in the same time ,or you need proper terminations?
 
Sorry I am not familiar with you are suggesting. do you mean like this?

Code: 
     process (clock)
     begin
          if (rising_edge(clock)) then
               this_ref_in <= ref_in;
          end if;
     end process;

and instead of using ref_in I use this_ref_in ?

Code: 
    CHAN2_ADPLL : all_digital_pll
    port map
    (
        clock   => clock,              -- 100 MHz clock
        reset   => reset,              -- global reset
        ref_in  => this_ref_in,             -- reference input signal
        sync_in => this_ndiv2_out,          -- channel 2 is the 2nd harmonics channel, need a n divider
        freq    => this_pll2_freq_tune      -- output tuning word
    );


Edit:
Thanks very much for pointing me in the right direction. I added a D flip-flop and now it works great!

Although I have my fingers crossed (hard to type) since I had to comment out a lot of the VHDL code to find this issue, I hope it doesn't come back after I uncomment them
 
Last edited:

i ment if signal integity is ok ?
also are you using it as dedicated global clock input , and use bufg ?
 

It is provided as a synchronisation signal for the ADPLLs. The global clock is a clock on the Altium nanoboard.
The signal itself is okay because I did a quick test where I measured the frequency of this signal with an Altium FPGA onboard frequency counter instrument and the number came up correctly.

I put a D flip-flop register right after the input port and then feed the output to the ADPLLs. As far as I can see, that fixed the problem... but only time will tell.
 

aobosong said:
It is provided as a synchronisation signal for the ADPLLs. The global clock is a clock on the Altium nanoboard.
The signal itself is okay because I did a quick test where I measured the frequency of this signal with an Altium FPGA onboard frequency counter instrument and the number came up correctly.

I put a D flip-flop register right after the input port and then feed the output to the ADPLLs. As far as I can see, that fixed the problem... but only time will tell.
Click to expand...

yes, it makes sense.

also if you are also use it also as a clock source elsewere add a BUFG for this.

BUFG_INSTANCE_NAME : BUFG
port map (O => user_O, I => user_I);
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top