A
ahmadagha23
Guest
hi dear friends
I have an vhdl source code and i can compile and simulate it by activhdl but when I want to compile it by modelsim it get error from my vhdl code .why?
is there difference between vhdl by modelsim and activehdl?
thanks from your help.
I have an vhdl source code and i can compile and simulate it by activhdl but when I want to compile it by modelsim it get error from my vhdl code .why?
is there difference between vhdl by modelsim and activehdl?
thanks from your help.