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layout post simulation and the schematic simulation is different

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sw0ws1

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Hi all
my question is the post layout simulation is different from schematic simulation(eff=62% in schematic and eff=52% in post layout)??i have no idea what to do??
how can i modify the layout to fit the schematic simulation??
thanks in advance
 

Hi,

I don't think you can. Post layout simulation tends to include all the parasitics RC. The only solution is:
1. Over-design and put more margins during schematic sim
2. Move to a better technology node if you are at the limit of your current technology.
3. Trade-off yield and throw away chips that failed the eff requirement.

narfnarf
 

sw0ws1 said:
Hi all
my question is the post layout simulation is different from schematic simulation(eff=62% in schematic and eff=52% in post layout)??i have no idea what to do??
how can i modify the layout to fit the schematic simulation??
thanks in advance
Click to expand...
efficiency of what type of design would be helpful to know
You can always annotate separately caps and resistors and see which are the problem (well sometimes you need both at once)
once you have the type of parasitic that is causing trouble, the strategy to hunt down the problem will depend on the design but in general you can try to extract smaller portions of the design, you can use the extraction tool to sort the nets by parasitic size, compare the OP of important devices, look at p/g connections with high currents, etc
 

That's kind of the whole point of layout based simulations -
to show you the effects of things you didn't express in the
schematic.

How you -should- fix it, is to put the missing details into
the schematic. Like parasitic capacitances or whatever.
The layout result is more likely realistic and if you don't
like near-reality, the real reality will suit you even less.
Like just wait until you add packaging effects.
 

RC parasite will reduce efficiency. It is normal.
However, if you want reduce its influence, you should post schematic for analysis.
 

The action depends on design!
What exactly do you mean by eff?

Find out what in layout capacitance is affecting the performance. This may be some particular node having more capacitance or between two nodes there is large cap, which circuit is not able to drive.
In such cases, either route such signals which are parasitic sensitive(e.g. Clock, input, output of a high speed block etc...) in highest metal level available. Or, move apart metals around it in layout. If still does not work, then increase width of transistor connected to that net. This will improve drive strength and you may get better result.

sw0ws1 said:
Hi all
my question is the post layout simulation is different from schematic simulation(eff=62% in schematic and eff=52% in post layout)??i have no idea what to do??
how can i modify the layout to fit the schematic simulation??
thanks in advance
Click to expand...

Regards,
Venky
 

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