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Icarus Verilog (iverilog) help needed

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rockgird

rockgird

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Hello,

I m trying to synthesis an asic code using iverilog ... but i m not able to simulate the filelist in one go ... it keeps showing that .h file is not found, and keep denying that the top file which i've defined is not the top file ...


Has any one faced this issue, i m using the iverilog version 0.9 on win xp.


Regards,
Ankit

PS: if any one has a link to any iverilog tutorial... please share ... :)
 

I m sorry ... that is no way related to my problem ...


I don't want to dived by 7 ... !! i have problem compiling code ...

And i've already mentioned that I m running it on Windows ... liniux command won't work ...
 

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