FPGA -AVR 3.3 - 5 volt level converter

atmega8 logic thresholds

hi,

i am interfacing fpga with atmega16 microcontroller. fpga outputs are lvttl. but for these outputs to be sensed by the microcontroller i need a 3.3 - 5 volt level converter. how can i do that?

fpga outputs are 3.28 volt exactly. how can i do that??

thanks in advance...

io level converter

1. If FPGA output are 5V tolerant - you can use it with 5V uC.

2. The best way is using atMega16L with supply 3.3V

level converters in fpga

thanx 4 the reply...

1. I am using XUP Virtex II pro development board,which is a EDA board and it contains a VIRTEX II PRO chip in it along with the other peripherals.
now we can get the digital outputs from the expansion ports of the board,which are tied to LVTTL standard only. I hav checked through multimeter and CRO ,that it is giving 2.98 v only for logic 1. Now, for the microcontroller to sense logic 1 it must be greater than 3.3 v. Thats why i need a level converter for LVTTL to CMOS/TTL.
FPGA cannot hav output of 5 v for logic 1. Though it can supply 5 v and 3.3 vas Vcc(we can use it anywhere) from 2 different i/o pin. but the data bits are 2.98 v for logic 1.

i think i hav stated my problem elaborately enough....

looking 4 help...

level converter

Try this online tool: **broken link removed**. It helps you pick the level-shifter IC.

Re: level converter

Strictly speaking, ATmega requires 0.6 * VCC minimum high level, which is 3.0V at 5.0V VCC. You should be able to achieve this voltage with 3.3V powered FPGA IO in general, but apparently, the output voltage is lower at your board. One may also specify an additional margin for higher noise immunity. Typically, but not guaranteed by design, the ATmega input threshold can be expected near to 0.5 * VCC.

You can use any TTL compatible 5V supplied logic, e. g. HCT, AHCT as a level shifter. It has a specified mimimum high level of 2.0 V, which gives a sufficient noise margin with 3.3V or 3.0V IO banks.

As another point, if the Virtex board don't has input clamping, the even more problematic interface is ATmega to FPGA, cause 5V must be expected to damage the FPGA inputs.