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I have a 54 MHz double-speed multiplexed D1 video interface.

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spktu

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saa7129 design

I have a 54 MHz double-speed multiplexed D1 video interface.
I need to split it into two separate channels : each a standard CCIR656 @ 27 Mhz.
Did anybody had the same problem and solved it?
Are there any available Opencores or IPs for such a task?
 

ccir656 54mhz

What is a "54 MHz double-speed multiplexed D1 video interface" ? Does it mean you have 2 video streams that are multiplexed at twice the speed (2 times 27MHz) OR that you have a progressive (not interlaced) video stream at 54MHz that you want to convert at 27MHz?

Can you tell me more on your video source? What equipment generates it? Is there a SMPTE standard?

TurboPC
 

d1 video interface

These are TWO CCIR656 ( with SAV and EAV embedded ) video streams that are multiplexed at twice the speed (2 times 27MHz).
They are taken from a part of a scheme ( from a previous design ), which was intended for SAA7129 PAL encoder.
SAA7129 requires exactly "54 MHz double-speed multiplexed D1 video interface".
I have to ( in the current design ) bypass SAA7129 and to split this 54 Mhz stream into two separate streams : each a standard CCIR656 @ 27 Mhz.
I cannot change the previous part of the scheme ( which supplies this 54 Mhz stream ).
 

why 54mhz, video interface

I had a look at the SAA7129 spec. To me it looks like the input clock is at 27MHz and the data input port is at twice the input frequency. The data on the rising edge seems to be one D1 stream and the data on the rising edge is the other D1 stream.

To bypass the SAA7129, it seems you need only to latch the input stream on the rising edge and the other on the falling edge. This can be done with 2 8-bit flip-flops and an inverter or you can use a small CPLD. A CPLD is a better solution if the setup/hold are small. Otherwise, a very fast (clock) inverter may be required for the second 8-bit FF.

For the output streams to be CCIR656 compliant, you need the SAV/EAV codes to be present in both multiplexed stream at the input.
 

What CPLD would You recommend to do this kind of job?

That's right - the clock is 27Mhz ( not 54 Mhz ).
The data on the rising edge is one D1 stream and the data on the rising edge is the other D1 stream.

Of course, CPLD is a much better solution.
Actually, I was asking for smth like that.
I am not very familiar with that kind of stuff :cry:
What CPLD ( and what software to design it ) would You recommend to do that kind of job?
:?:
 

In case my previous explanation was not clear, here's what I meant to separate the 2 stream:

process stream_1 (clock)
begin
if clock'event and clock='1' then
d1_stream1_out <= dual_D1_in;
end if;
end process;

process stream_2 (clock)
begin
if clock'event and clock='0' then
d1_stream2_out <= dual_D1_in;
end if;
end process;
 

Re: I have a 54 MHz double-speed multiplexed D1 video interf

Your explanation was absolutely clear.
That simple program, that You posted - what is its purpose?
Is it in some kind of a CPLD programming language?
Please excuse my illiteracy in that area :oops:

What CPLD ( and what software to design it ) would You recommend to do that kind of job?
 

spktu:

The simple program is VHDL code to latch the dual D1 input and produce two D1 stream output, each latched on the rising or falling edge. Yes! It is a design language for CPLDs, FPGAs and ASICs.

If you ane not familiar with CPLD, you may want to read about them on Elektroda (do a search) or go directly to some CPLD manufacturers like www.altera.com , www.xilinx.com, ...
They offer also software Web version to design your CPLD. You will also need a way to program them using JTAG or a programmer...

If you are unfamiliar with CPLDs, I suggest you use discreet components (latches and inverter). You will get your result faster. Price will be the same, but your PCB board space will be slightly bigger.

Good luck!

TurboPC
 

Re: I have a 54 MHz double-speed multiplexed D1 video interf

Hi spktu,

If you don't know anything about CPLD, may be it will be easier for you to use 2 simple octal latches and a not gate. So you will make exactly the design described in turboPC vhdl code, without tools for synthesis/route and configure a CPLD.

:idea:
 

Why Octal D-Type Latch ( SN74ALS373 )?

Why Octal D-Type Latch ( SN74ALS373 )?
Why an Octal D-Type Edge Triggered (Flip-flops ( SN74ALS374 ) is no good for this kind of job?
 

Re: Why Octal D-Type Latch ( SN74ALS373 )?

spktu said:
Why Octal D-Type Latch ( SN74ALS373 )?
Why an Octal D-Type Edge Triggered (Flip-flops ( SN74ALS374 ) is no good for this kind of job?
Click to expand...

You are right. Use an Octal D-Type Edge Triggered (Flip-flops ( SN74ALS374 ). A latch won't work! Just make sure you choose the proper family to ensute it works at 54MHz with the proper setup&hold timing.

TurboPC
 

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