Mirzaaur
Member level 2
hi all;
in my design I generate local clock using DCM and provide a clock on output of the virtexII.
when i try to create timing constraints after synthesis using constraints editor, I don't get the clock signals there. but some other signal which are not clock they are listed as clock. I checked these signals are detected for the transition at any level.
HOW I CAN TELL XST - SYNTHESIZER NOT TO USE CERTAIN SIGNALS AS CLOCK?
thankful for any hint or tip.
mirza
in my design I generate local clock using DCM and provide a clock on output of the virtexII.
when i try to create timing constraints after synthesis using constraints editor, I don't get the clock signals there. but some other signal which are not clock they are listed as clock. I checked these signals are detected for the transition at any level.
HOW I CAN TELL XST - SYNTHESIZER NOT TO USE CERTAIN SIGNALS AS CLOCK?
thankful for any hint or tip.
mirza