Integrating HDL modules and CoreGenerator parts using EDK

using coregen modules

I've been looking at this today and have found several work-flows but I'm still confused.

I need to do two things, the first of which is not critical as I could write a MicroBlaze software driver and bit-bang. Using a HDL module would be a bonus though, and may speed things up if I use interrupts. I think these things are essentially the same from the view of getting them to work with a MB and EDK.

1. Add a Verilog HDL module to the MB in the EDK.
2. Add a CoreGenerator module (a FFT core) to the MB in the EDK.

Do I have to put these into ISE and create a kind of port translation to interface them to the On-chip Peripheral Bus? Do I put both the modules into some new project in ISE with a top level that does the mapping?

Does anyone have any concise information on this topic please?

Regards,

Rob

how to import the coregen generated core to edk

I think a "Create Custom Peripheral" in EDK will help you. You should also study the IPIF documentation.

hdl wrapper

The Create Custom Peripheral wizard generates VHDL only, I have only used Verilog HDL.

Is there a way around this or is VHDL the only way?

Has anyone managed to get a CoreGenerator FFT core successfully into an EDK project or am I going about that the wrong way?

add edk core

I see now that I have to make compliant controllers to interact with processor buses, FSL and OPB. The controller abstracts the cores from the CPU rather than them being connected directly.

Now I nope I can learn enough VHDL in a matter of days . There doesn't seem to be much Veriog support for this in the tools.

edk custom peripheral verilog

Hi,
You can write your verilog code without any problem.
Then you should synthesize your code and add the result (.edf or .edn) to your project.
In "create and import peripheral" option use "create" (if you want to add your ip to OPB or FSL Bus) and choose your needed options. Created VHDL file named user_logic.vhd has sample codes. delete all codes except port declarations ( use vhdl as a wrapper).
then use "create and import peripheral" for the second time and choose import. add created IP and check netlist(.edn or .edf) and then add your .edn to the project.
I try this and it works properly. hopefully it works for you.

create netlist for custom peripheral ngc

I have two modules that I need, one is from CoreGen, jumping in at the deep end here but I don't really have much choice .

Do I have this flow correct?

Build my FFT part using CoreGen.

Use XPS "Create or Import Peripheral" to make a template that will be attached via FSL or OPB.

I get a bit lost at this stage...

Does the template HDL generated by XST instantiate the FFT that CoreGen made?

Do I have to then connect the ports in the template HDL to the relevant ones of the FFT?


I have had a look at the Xilinx documentation and found this to be more or less exactly what I want:

xilinx.com/support/documentation/application_notes/xapp529.pdf

Page 10 shows the bit that I'm most interested in but it does not go as far as to explain what "idct_core.vhd" does and I have not had any exposure to VHDL and therefore can't tell from their example code.

hdl parts

About "Create and import peripheral", maybe this could help:
https://www.xilinx.com/support/documentation/application_notes/xapp967.pdf


coregen output (.ngc or .edn) should be added to your created template.
also you need hdl wrapper.
Your top module(FFT or any) ports made your wrapper.
then it will be instantiated.

And about xapp529, I think it doesn't tell anything about coregen-made core. Maybe i should read it carefully

integrating coregen file

App note xapp529 doesn't cover CoreGen modules specifically.

I think I just want FSL.

The steps I have taken:

Used CoreGen to make a core project, changed design entry to Verilog, selected "Create Netlist Wrapper with IO pads" (I don't know if I need that). That gave me the following files.

# Output products list for <FFTCore>
FFTCore.ngc
FFTCore.v
FFTCore.veo
FFTCore.xco
FFTCore_flist.txt
FFTCore_padded.edn
FFTCore_xmdf.tcl
wrap_TRIG_ROM.mif

I then used XPS Peripheral Wizard to create a template (to my main project). Called it fft0, added FSL, selected Verilog. This created some files and the HDL, fft0.v.

What is the next step?

Where and how do I connect the FFTCore to the FSL enabled template?

Many thanks for the help, I'm confused about this .

import coregen

Hi,

I think you shouldn't check "Create Netlist Wrapper with IO pads" because FFT is a module in your whole design and it's ports are not IO pins, am I right?

Ok, about create peripheral in XPS: Checking verilog option for creating fft.v maybe doesn't work properly. For me it doesn't work anyway. I found that my verilog codes doesn't implemented in this way. But maybe it was bacause of doing s.th. wrong. so I do s.th. else

if you don't check this option and fft.vhd created, you can add your core ports from fft.vho (should be created by coregen).

then you should use import peripheral and use the name fft you chosen before. check HDl and netlist and add fft.edn(from coregen) and fft.vhd(in pcores folder that you add your ports to it) when asked.

edk verilog wrapper

Oh! The IO wrapper is to make the IP accessible from outside the FPGA?

I do need that for one of my cores, only certain pins though, the rest can stay internal.

I've had a bit progress, I started from the software side. I made a template for FSL and imported it and have been using the sample HDL to try to figure out what I need to do with it.

I'm going to try putting the ADC driver from this thread into a FSL template tomorrow. That will need some of the ports to be externally routed to some GPIO pins (I think that was going to be my next question ).

I think the FSL bus framework is working anyhow, I seem to be able to write a value to it and then read it back using the microblaze_bwrite_datafsl type functions.

edk mif

if you have from core generator a DDR module. how you insert all the vhdl files. you doing it with BBD?

add verilog to edk

Hi,
Can you explain your question? I can't understand you

coregen modules in custom ip edk

hello

I am trying to insert a Micron DDR interface controller for Spartan3 familly gererated from coregen. the memory generated correctly, i am running the ise_flow.bat in order to perform synthesis and place and route. since i am trying to import this core to XPS (ver.9.1i) user repository and interfacing the OPB bus but i can't.
I have search the web but couldn't find a step by step guide for memory how to do it. Found general .pdfs about "create import peripheral" but didnt found them helpfull.