VHDL: Truncate signed to std_logic_vector

signed to std_logic_vector

I need to synthesize a DCT core to a Spartan3E FPGA and have the following problem:

The core uses a Rom for the DCT coefficients and calculates them like this.

type ROM_TYPE is array (0 to (2**ROMADDR_W)-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( AP )(ROMDATA_W-1 downto 0),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP+AP+AP ),
std_logic_vector( AP+AP+AP+AP ),
.......etc.


AP is a constant:

constant AP : SIGNED(ROMDATA_W-1 downto 0) := "00" & "010110101000";

How can I truncate AP+AP to the 14bits needed inside the typecasting command? The problem is that the additions AP+AP, AP+AP+AP etc overflow to >14bits and the core cannot be synthesized.

Any ideas anyone?

std_logic_vector signed

i think this is a case when you are trying to fit a bigger tube for your tire.

vhdl truncate

You are right but this is not my code this is a DCT core ready and verified from www.opencores.org and I am trying to synthesize it in order to adjust it to my project. That's why I am asking. Perhaps someone has encountered this kind of typecasting and has a solution to propose.

vhdl signed to std_logic_vector

well in this case i would use a function to do the truncation , and put it in my package.

vhdl truncate std_logic_vector

I didn't try, but there should be several options to size the constants: an AND mask, a conv_unsigned(), a mod operator, a user defined function.