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How to Synch. two Diff clock.

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dinesh.4126

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hi,
In a design i am having two clock.clk1 is of 100khz and clk2 is off 50khz and we are talking data at posedge of clk1 and using this data at posedge of clk2,so how to syn. these clks so that data at posedge of clk2 is not lost.give me some hint. how to tackle clock sync. problem B/w clocks,

Regards,
Dinesh
 

Are the two clocks locked in phase? Or are they independently generated? Moving from a higher speed clock to a slower speed clock can be a problem. The absolute best case is that you can update data on the higher speed clock at only the lower clock's rate. Therefore, the higher speed clock can only update the data only every other cycle. In practise, you could still lose data at this rate, if you just miss the setup time on the lower speed clock.

For single bit-wide transfers, you can be assured of capturing the data if you hold the high speed data for three or more clocks. When transferring a wide bus, this still works, however you are not guaranteed that all bits of the bus will transition on the same clock cycle.

If the clock edges are fairly well aligned, I have had good success with moving the data from the positive edge to the negative edge of the higher speed clock before crossing the clock domain. This increases the setup time of the transfer and holding the data for two cycles should insure that the data makes it across the clock domains.

--- Steve
 

I expect the clocks are asynchronous or it wouldn't be a problem. In this case, I would use a FIFO to transfer the data between clock domains.
 

Hi,
What is the specific reason behind to Hold the data for three or more clock pulse??
Why not Two clock???
What I get is that in a code of Synch. of clks I have to give dealy of three or more clk pulse (faster clk) and then data is Captured at slow clk so that no data loss is their during grabing of data at slower clk.Am I right or not??
If the edge of two clocks are not aligned then how to tackle this situation??

----
Dinesh
 

the best thing is to up sample the 100khz.

you can use pll to multiply the 50khz .

then recover the signal and dff it with the 50khz which should be phase alligned to the upsampling clock.
 

You need to provide more information so as to get further details on the answer.

1) Is the data on the 100khz always changing at every clock? Is there a new data at every clock rise edge?

2) If not what is the duration for which there is valid data on the 100khz line.

Think of an asynchronous FIFO design.
 

Hi,
1)Data is changing at every rising of clk(100khz).
2)We have to use this data to another Design which is operating at lower rate(50khz).
Interviewer asked me how you will tackle this problem so that no loss of data is occur at lower Freq. in our design without using PLL,DCM.
 

If the data is changing at every rising edge of 100KHZ clock, then you must widen the bus when going to a 50KHZ domain! Otherwise data is arriving twice as fast as its leaving.

For the clock, I think they were looking for a answer of "the 50kHZ clock must be generated from the 100KHZ by a divider. " This insures that the 50KHZ is always later in phase than the 100KHZ and allows you to predict setup and hold times.
 

Hi,
Interviewer ask me this question by showing these waveform and expecting from me what you will do when you take same Data at CLK2(50khz).
Because at CLK2 Data will lost.
what I think is that we have to generate some intermediate signal from clk,so that that data at clk2 not be lost.
Am I thinking in right way?
and also CLK1(100KHZ).
 

if ignoring the skew isues :

i think what he really wanted you to say is that you will use 2 bit bus as output with the 50khz clock, i.e to demux the data1 input !

so you use the clock2 as selector to 1:2 demux device that select the data1 input !!!


best regards !
 

This is getting nothing....See even though you sync your two clocks,the data is based upon the clk1 which is twice as fast as clk2@50MHz, so for every +ve edge of clk2 you lose one data bit..I am not so exact but maybe a way close to this could be like taking a complement of this clk2 and checking for rising edge of clk2 and clk2_inv. With respect to these 2 clks@50MHz, you get two data bits for one clk2 period or 1 data bit for 1 clk1 period....Thus
If rising_edge(clk2) THEN
data_buff1 <= DATA;
endif;
If rising_edge(clk2_inv) then
data_buff2 <= DATA;
end if;
Upto this point, you are reading 100MHz data rate with two 50MHz clock(invt and non-invt). For 1 single 50MHz clock cycle period, you will get two 100MHz data bits in this case.One data in data_buff1 and another in data_buff2. I once used this technique to recover the clock for Manchester coding where the recieved coded data will have twice the total bandwidth of our data rate....But I'm not sure how you could proceed from this point onward!....
 

Asynchronous FIFO I am not fully assure will it be right Answer because if we use clk1(100Khz) for writing operation and clk2(50khz) for reading operation and clk1 is faster so I think their might be problem of Data over written.

Am I right or wrong??
 

Yes, in theory you can lose data. However, if the data stream is not continuous and the FIFO is deep enough, it will not wrap around.
If you want continuous data AND fully async clocks, then the solution is to use a FIFO with different bus widths on the input and output. This allows you to extract the data at the same rate as you put it in. Data would come out at 1/2 speed, but be twice as wide.
---- Steve
 

I have one more doubt in Asynchronous FIFO in this case clk1(100khz) is twice of clk2(50khz),therefore Data width is Double in read case,suppose if clk1 is of 150 khz and clk2 will be of 40 khz(when two clk is not multple),then in that case asyn. FIFO will work or not???
 

shawndaking said:
if ignoring the skew isues :

i think what he really wanted you to say is that you will use 2 bit bus as output with the 50khz clock, i.e to demux the data1 input !

so you use the clock2 as selector to 1:2 demux device that select the data1 input !!!


best regards !
Click to expand...

https://en.wikipedia.org/wiki/SerDes
 

Within programmable logic like FPGAs, you have lots of options for bus widths. Lets say that I make the slower clock's bus 10 times as wide as the faster clock. It will still work because the FIFO has an empty flag. The slower clock with the very wide bus would then need to poll the empty flag and only attempt to extract data when the FIFO is not empty. HereI am able to extract data much faster than it can be written into the FIFO from the front-end. Therefore, I have to monitor the FIFO status and only extract data when there is something to get!
 

Hello friends!
I think I have a solution to this question!.....
Step 1: Let the clk of 50KHz be CLK_50KHZ and it's complement be CLK_INV50KHZ.
Step 2: Now shift the CLK_INV50KHZ by a delay of 1/4 of the ON time of CLK_50KHZ.
Step 3: Now that you have obtained 2 50KHz sqrs with one wave, 180Deg out of phase along with a shift of 1/8 of CLK_50KHZ.
Step 4: Take XOR between these two clks.
Step 5: Now what you get is a train of trigger pulse for both ON and OFF time of your CLK_50KHZ!....Use this new XORed clk to fed your device to read the data from the 100KHz data bus...The data you read is at 100Kbps rate can now be sampled at time of 1\8th of it's 100KHz clk.So no need to worry about data skipping!.....Also this makes no need for any other logic and it's a simple.! I once used this logic for recovering data from Manchester coding which has frequency exactly double of the data rate!....There you go!...If there is mistake or flaws, please correct me!..
 

shift the CLK_INV50KHZ by a delay of 1/4 of the ON time of CLK_50KHZ?
 

The time period for 50KHz clk is 20us, therefore desing a delay of 5us and then invert the signal and use that for xoring.IS it clear now?
 

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