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Memory: Small problem

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sameem_shabbir

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I have copied language templates provided inpri=oject navigator to make a block ram

Are there any timming constraints in this block ram or it is just a reg array.

Now should i give the data and upgrade the addr at the positive edge clk
or should i upgrade the addr at negedge clk and give the data at posedge.

Which is going to work better
 

I guess no timming constraints except read or write. First place address and then enable read\write.So far as I used the block ram,the output will always be latched(from Block RAM address point). So if you give new address with read enabled,it automatically latches that address's data.
 

you can get the timing spec from fpga datasheet., and you better launch and sample at the same edges.
 

You mentioned Project Navigator, so I assume you are referring to a modern Xilinx FPGA. The Block RAM is a friendly synchronous device that uses the positive clock edge. It behaves like a big register array, although the clock-to-output delay is usually slower than a slice flop. In most projects you don't have to worry much about the block RAM's precise timing details, but if you need them see the "switching characteristics" section of the FPGA data sheet.

Some Xilinx FPGAs provide special Block RAM features such as an optional output register that improves the clock-to-output delay. Read about the various features in your specific FPGA User Guide.
 

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