DSD
Newbie level 3
There are two familiar naming styles for identifiers (signal names, port names, module names etc) in verilog HDL.
1. Use lower case letters for all identifiers, for example, rx_flow.
2. Mix lower case letters and upper case letters for all identifiers, for example, RxFlow.
Which style do you use in your design? Why?
I prefer the second style because it is clearer and uses less letters.
1. Use lower case letters for all identifiers, for example, rx_flow.
2. Mix lower case letters and upper case letters for all identifiers, for example, RxFlow.
Which style do you use in your design? Why?
I prefer the second style because it is clearer and uses less letters.