Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

When does the SRAM and DRAM need redundancy

Status
Not open for further replies.

greensand

Newbie level 4
Joined
Aug 21, 2004
Messages
7
Helped
0
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
60
Hi, everybody,
I am not sure about the redundancy of SRAM and DRAM.
When you need add redundancy for SRAM and DRAM, How big the SRAM and DRAM?
and how to realize the redundancy?
by laser fuse or electrical programmable fuse?
I expect the expert may tell me.
thanks
 

The simple answer is: whenever the percentage of die defects due to SRAM failure becomes unnaceptable (this depends on project and target market/volume). Once you pick the ppm failure rate due to SRAMs bit cells/bit lines/word lines, given the defect density per mm^2 of SRAM (these are provided by your foundry) you can calculate how many redundant rows/columns you need to build in to hit your failure rate target.

Added after 1 minutes:

Also, redundancy selection bits are usually implemented using e-fuse bits, laser fuses are lots of money so it is tough for them to pay off vs. just letting the rams fail.
 
Thanks eternal_an for your excellent reply.
the e-fuse you mentioned is electrical programmable fuse?
could you provide some paper about fuse or redundancy for reference?
Thanks.

my mail: cloudheron@yahoo.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top