Jiggle
Newbie level 1
Beginner question re. behaviour of synthesised VHDL and propagation delay of process
I come from a software development background with some basic electronics knowledge and have become interested in learning VHDL.
Please can you help me with my understanding of the synthesised VHDL behaviour.
I assume that the two processes below are totally asynchronous to each other if synthesised into real hardware.
Is this a correct assumption?
Given that, if I were driving the following (clk, res, sig_in) via IO pins I would need to make sure that sig_in has a settled value (propagation delay sig_in to sig_eval) before transitioning the clock high to set the sig_out to the sig_eval value (res is 0).
If I were driving these (clk, res, sig_in) internally via another VHDL process, would the VHDL do some magic with synchronising/ordering of the processes or would this be totally asynchronous too and the two processes below run at some point because of their sensitivity lists but the order unknown (dependent on synthesised implementation)?
Thanks,
Justin...
I come from a software development background with some basic electronics knowledge and have become interested in learning VHDL.
Please can you help me with my understanding of the synthesised VHDL behaviour.
I assume that the two processes below are totally asynchronous to each other if synthesised into real hardware.
Is this a correct assumption?
Given that, if I were driving the following (clk, res, sig_in) via IO pins I would need to make sure that sig_in has a settled value (propagation delay sig_in to sig_eval) before transitioning the clock high to set the sig_out to the sig_eval value (res is 0).
If I were driving these (clk, res, sig_in) internally via another VHDL process, would the VHDL do some magic with synchronising/ordering of the processes or would this be totally asynchronous too and the two processes below run at some point because of their sensitivity lists but the order unknown (dependent on synthesised implementation)?
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 signal clk: std_logic; signal res: std_logic; signal sig_eval: std_logic; signal sig_out: std_logic; signal sig_in: std_logic; -- ... process(sig_in) begin sig_eval <= not sig_in; -- Could be a lot more complex (longer time) end process; -- ... process(clk, res) begin if(reset = '1') then sig_out <= '0'; elsif rising_edge(clk) then sig_out <= sig_eval; end if; end process
Thanks,
Justin...