analogdesignlove
Newbie level 6
Hi, I am new to primetime. I got the netlist file and gave the search path for the design. But my design is a .sv file. How can I use that in primetime.
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Can you tell me how to instantiate single ported memory macro based on a particular technology library?
Error: Width mismatch on port 'addr_i' of reference to 'sp_ram_bank' in 'sp_ram_wrap_RAM_SIZE32768_DATA_WIDTH32'. (LINK-3)
Error: Unable to match ports of cell core_region_i/data_mem/sp_ram_bank_i ('sp_ram_bank') to 'sp_ram_bank_NUM_BANKS8_BANK_SIZE1024'. (LINK-25)
Error: Width mismatch on port 'addr_i' of reference to 'sp_ram_bank' in 'sp_ram_wrap_RAM_SIZE32768_DATA_WIDTH32'. (LINK-3)
Error: Unable to match ports of cell core_region_i/instr_mem/sp_ram_wrap_i/sp_ram_bank_i ('sp_ram_bank') to 'sp_ram_bank_NUM_BANKS8_BANK_SIZE1024'. (LINK-25)
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 `include "config.sv" module sp_ram_wrap #( parameter RAM_SIZE = 32768, // in bytes parameter ADDR_WIDTH = 32, parameter DATA_WIDTH = 32 )( // Clock and Reset input logic clk, input logic rstn_i, input logic en_i, input logic [ADDR_WIDTH-1:0] addr_i, input logic [DATA_WIDTH-1:0] wdata_i, output logic [DATA_WIDTH-1:0] rdata_o, input logic we_i, input logic [DATA_WIDTH/8-1:0] be_i, input logic bypass_en_i ); `ifdef PULP_FPGA_EMUL xilinx_mem_8192x32 sp_ram_i ( .clka ( clk ), .rsta ( 1'b0 ), // reset is active high .ena ( en_i ), .addra ( addr_i[ADDR_WIDTH-1:2] ), .dina ( wdata_i ), .douta ( rdata_o ), .wea ( be_i & {4{we_i}} ) ); // TODO: we should kill synthesis when the ram size is larger than what we // have here `elsif ASIC // RAM bypass logic logic [31:0] ram_out_int; // assign rdata_o = (bypass_en_i) ? wdata_i : ram_out_int; assign rdata_o = ram_out_int; sp_ram_bank #( .NUM_BANKS ( RAM_SIZE/4096 ), .BANK_SIZE ( 1024 ) ) sp_ram_bank_i ( .clk ( clk ), .rstn_i ( rstn_i ), .en_i ( en_i ), .addr_i ( addr_i ), .wdata_i ( wdata_i ), .rdata_o ( ram_out_int ), .we_i ( (we_i & ~bypass_en_i) ), .be_i ( be_i ) ); `else sp_ram #( .ADDR_WIDTH ( ADDR_WIDTH ), .DATA_WIDTH ( DATA_WIDTH ), .NUM_WORDS ( RAM_SIZE ) ) sp_ram_i ( .clk ( clk ), .en_i ( en_i ), .addr_i ( addr_i ), .wdata_i ( wdata_i ), .rdata_o ( rdata_o ), .we_i ( we_i ), .be_i ( be_i ) ); `endif endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 pulpino_top // Copyright 2017 ETH Zurich and University of Bologna. // Copyright and related rights are licensed under the Solderpad Hardware // License, Version 0.51 (the “License”); you may not use this file except in // compliance with the License. You may obtain a copy of the License at // [url]https://solderpad.org/licenses/SHL-0.51[/url]. Unless required by applicable law // or agreed to in writing, software, hardware and materials distributed under // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR // CONDITIONS OF ANY KIND, either express or implied. See the License for the // specific language governing permissions and limitations under the License. `include "axi_bus.sv" `include "debug_bus.sv" `define AXI_ADDR_WIDTH 32 `define AXI_DATA_WIDTH 32 `define AXI_ID_MASTER_WIDTH 2 `define AXI_ID_SLAVE_WIDTH 4 `define AXI_USER_WIDTH 1 module pulpino_top #( parameter USE_ZERO_RISCY = 0, parameter RISCY_RV32F = 0, parameter ZERO_RV32M = 1, parameter ZERO_RV32E = 0 ) ( // Clock and Reset input logic clk /*verilator clocker*/, input logic rst_n, input logic clk_i, input logic clk_standalone_i, input logic testmode_i, input logic fetch_enable_i, input logic scan_enable_i, //SPI Slave input logic spi_clk_i /*verilator clocker*/, input logic spi_cs_i /*verilator clocker*/, output logic [1:0] spi_mode_o, output logic spi_sdo0_o, output logic spi_sdo1_o, output logic spi_sdo2_o, output logic spi_sdo3_o, input logic spi_sdi0_i, input logic spi_sdi1_i, input logic spi_sdi2_i, input logic spi_sdi3_i, //SPI Master output logic spi_master_clk_o, output logic spi_master_csn0_o, output logic spi_master_csn1_o, output logic spi_master_csn2_o, output logic spi_master_csn3_o, output logic [1:0] spi_master_mode_o, output logic spi_master_sdo0_o, output logic spi_master_sdo1_o, output logic spi_master_sdo2_o, output logic spi_master_sdo3_o, input logic spi_master_sdi0_i, input logic spi_master_sdi1_i, input logic spi_master_sdi2_i, input logic spi_master_sdi3_i, input logic scl_pad_i, output logic scl_pad_o, output logic scl_padoen_o, input logic sda_pad_i, output logic sda_pad_o, output logic sda_padoen_o, output logic uart_tx, input logic uart_rx, output logic uart_rts, output logic uart_dtr, input logic uart_cts, input logic uart_dsr, input logic [31:0] gpio_in, output logic [31:0] gpio_out, output logic [31:0] gpio_dir, output logic [31:0] [5:0] gpio_padcfg, // JTAG signals input logic tck_i, input logic trstn_i, input logic tms_i, input logic tdi_i, output logic tdo_o, // PULPino specific pad config output logic [31:0] [5:0] pad_cfg_o, output logic [31:0] pad_mux_o ); logic clk_int; logic fetch_enable_int; logic core_busy_int; logic clk_gate_core_int; logic [31:0] irq_to_core_int; logic lock_fll_int; logic cfgreq_fll_int; logic cfgack_fll_int; logic [1:0] cfgad_fll_int; logic [31:0] cfgd_fll_int; logic [31:0] cfgq_fll_int; logic cfgweb_n_fll_int; logic rstn_int; logic [31:0] boot_addr_int; AXI_BUS #( .AXI_ADDR_WIDTH ( `AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( `AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( `AXI_ID_SLAVE_WIDTH ), .AXI_USER_WIDTH ( `AXI_USER_WIDTH ) ) slaves[2:0](); AXI_BUS #( .AXI_ADDR_WIDTH ( `AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( `AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( `AXI_ID_MASTER_WIDTH ), .AXI_USER_WIDTH ( `AXI_USER_WIDTH ) ) masters[2:0](); DEBUG_BUS debug(); //----------------------------------------------------------------------------// // Clock and reset generation //----------------------------------------------------------------------------// clk_rst_gen clk_rst_gen_i ( .clk_i ( clk ), .rstn_i ( rst_n ), .clk_standalone_i ( clk_standalone_i ), .testmode_i ( testmode_i ), .scan_i ( 1'b0 ), .scan_o ( ), .scan_en_i ( scan_enable_i ), .clk_o ( clk_int ), .rstn_o ( rstn_int ) ); //----------------------------------------------------------------------------// // Core region //----------------------------------------------------------------------------// core_region #( .AXI_ADDR_WIDTH ( `AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( `AXI_DATA_WIDTH ), .AXI_ID_MASTER_WIDTH ( `AXI_ID_MASTER_WIDTH ), .AXI_ID_SLAVE_WIDTH ( `AXI_ID_SLAVE_WIDTH ), .AXI_USER_WIDTH ( `AXI_USER_WIDTH ), .USE_ZERO_RISCY ( USE_ZERO_RISCY ), .RISCY_RV32F ( RISCY_RV32F ), .ZERO_RV32M ( ZERO_RV32M ), .ZERO_RV32E ( ZERO_RV32E ) ) core_region_i ( .clk ( clk_int ), .rst_n ( rstn_int ), .testmode_i ( testmode_i ), .fetch_enable_i ( fetch_enable_int ), .irq_i ( irq_to_core_int ), .core_busy_o ( core_busy_int ), .clock_gating_i ( clk_gate_core_int ), .boot_addr_i ( boot_addr_int ), .core_master ( masters[0] ), .dbg_master ( masters[1] ), .data_slave ( slaves[1] ), .instr_slave ( slaves[0] ), .debug ( debug ), .tck_i ( tck_i ), .trstn_i ( trstn_i ), .tms_i ( tms_i ), .tdi_i ( tdi_i ), .tdo_o ( tdo_o ) ); //----------------------------------------------------------------------------// // Peripherals //----------------------------------------------------------------------------// peripherals #( .AXI_ADDR_WIDTH ( `AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( `AXI_DATA_WIDTH ), .AXI_SLAVE_ID_WIDTH ( `AXI_ID_SLAVE_WIDTH ), .AXI_MASTER_ID_WIDTH ( `AXI_ID_MASTER_WIDTH ), .AXI_USER_WIDTH ( `AXI_USER_WIDTH ) ) peripherals_i ( .clk_i ( clk_int ), .rst_n ( rstn_int ), .axi_spi_master ( masters[2] ), .debug ( debug ), .spi_clk_i ( spi_clk_i ), .testmode_i ( testmode_i ), .spi_cs_i ( spi_cs_i ), .spi_mode_o ( spi_mode_o ), .spi_sdo0_o ( spi_sdo0_o ), .spi_sdo1_o ( spi_sdo1_o ), .spi_sdo2_o ( spi_sdo2_o ), .spi_sdo3_o ( spi_sdo3_o ), .spi_sdi0_i ( spi_sdi0_i ), .spi_sdi1_i ( spi_sdi1_i ), .spi_sdi2_i ( spi_sdi2_i ), .spi_sdi3_i ( spi_sdi3_i ), .slave ( slaves[2] ), .uart_tx ( uart_tx ), .uart_rx ( uart_rx ), .uart_rts ( uart_rts ), .uart_dtr ( uart_dtr ), .uart_cts ( uart_cts ), .uart_dsr ( uart_dsr ), .spi_master_clk ( spi_master_clk_o ), .spi_master_csn0 ( spi_master_csn0_o ), .spi_master_csn1 ( spi_master_csn1_o ), .spi_master_csn2 ( spi_master_csn2_o ), .spi_master_csn3 ( spi_master_csn3_o ), .spi_master_mode ( spi_master_mode_o ), .spi_master_sdo0 ( spi_master_sdo0_o ), .spi_master_sdo1 ( spi_master_sdo1_o ), .spi_master_sdo2 ( spi_master_sdo2_o ), .spi_master_sdo3 ( spi_master_sdo3_o ), .spi_master_sdi0 ( spi_master_sdi0_i ), .spi_master_sdi1 ( spi_master_sdi1_i ), .spi_master_sdi2 ( spi_master_sdi2_i ), .spi_master_sdi3 ( spi_master_sdi3_i ), .scl_pad_i ( scl_pad_i ), .scl_pad_o ( scl_pad_o ), .scl_padoen_o ( scl_padoen_o ), .sda_pad_i ( sda_pad_i ), .sda_pad_o ( sda_pad_o ), .sda_padoen_o ( sda_padoen_o ), .gpio_in ( gpio_in ), .gpio_out ( gpio_out ), .gpio_dir ( gpio_dir ), .gpio_padcfg ( gpio_padcfg ), .core_busy_i ( core_busy_int ), .irq_o ( irq_to_core_int ), .fetch_enable_i ( fetch_enable_i ), .fetch_enable_o ( fetch_enable_int ), .clk_gate_core_o ( clk_gate_core_int ), .fll1_req_o ( cfgreq_fll_int ), .fll1_wrn_o ( cfgweb_n_fll_int ), .fll1_add_o ( cfgad_fll_int ), .fll1_wdata_o ( cfgd_fll_int ), .fll1_ack_i ( cfgack_fll_int ), .fll1_rdata_i ( cfgq_fll_int ), .fll1_lock_i ( lock_fll_int ), .pad_cfg_o ( pad_cfg_o ), .pad_mux_o ( pad_mux_o ), .boot_addr_o ( boot_addr_int ) ); //----------------------------------------------------------------------------// // Axi node //----------------------------------------------------------------------------// axi_node_intf_wrap #( .NB_MASTER ( 3 ), .NB_SLAVE ( 3 ), .AXI_ADDR_WIDTH ( `AXI_ADDR_WIDTH ), .AXI_DATA_WIDTH ( `AXI_DATA_WIDTH ), .AXI_ID_WIDTH ( `AXI_ID_MASTER_WIDTH ), .AXI_USER_WIDTH ( `AXI_USER_WIDTH ) ) axi_interconnect_i ( .clk ( clk_int ), .rst_n ( rstn_int ), .test_en_i ( testmode_i ), .master ( slaves ), .slave ( masters ), .start_addr_i ( { 32'h1A10_0000, 32'h0010_0000, 32'h0000_0000 } ), .end_addr_i ( { 32'h1A11_FFFF, 32'h001F_FFFF, 32'h000F_FFFF } ) ); endmodule