Anachip
Member level 2
agc single op amp
Hi Guys,
I'm currently doing research on the AGC (Automatic Gain Control) Amplifer. While reading journals, i came to know that the AGC is consists of a Peak Detector, Comparator, Lossy Integrator and Low Pass Filter. I found out one circuit a part of AGC design which is comparator, integrator and low pass filter as per attached. But i'm still can't understand how does this circuit works. What must the value of Rf, Cf, Ro & Co to be designed if im desiging this circuit to work at 1.25Gbps. In the initial design, what is the dc voltage I need to set at the Vagc output. I'm connecting this Vagc output to the gate of NMOS which is parrallel with a resistor in order to control the gain. Meaning that, when my Vpeak is higher than my refernce voltage, my Vagc need to go high, thus it will turn the NMOS and the total gain will be reduced and vise versa. Please guide me to understand how to design this circuit. Thank you very much.
Anachip.
Hi Guys,
I'm currently doing research on the AGC (Automatic Gain Control) Amplifer. While reading journals, i came to know that the AGC is consists of a Peak Detector, Comparator, Lossy Integrator and Low Pass Filter. I found out one circuit a part of AGC design which is comparator, integrator and low pass filter as per attached. But i'm still can't understand how does this circuit works. What must the value of Rf, Cf, Ro & Co to be designed if im desiging this circuit to work at 1.25Gbps. In the initial design, what is the dc voltage I need to set at the Vagc output. I'm connecting this Vagc output to the gate of NMOS which is parrallel with a resistor in order to control the gain. Meaning that, when my Vpeak is higher than my refernce voltage, my Vagc need to go high, thus it will turn the NMOS and the total gain will be reduced and vise versa. Please guide me to understand how to design this circuit. Thank you very much.
Anachip.