Mucit23
Newbie level 3
Hi Friends
I am trying to make a simple spi module with verilog. After I get the
Enable signal, I want to send the 8 bit data in series.
I've never worked with a verilog before.
I wrote a simple code but I do not know how to generate the clock
signal.
this is my Code;
I will be glad if you help me. I'm just looking for a very simple
example of spi.
I am trying to make a simple spi module with verilog. After I get the
Enable signal, I want to send the 8 bit data in series.
I've never worked with a verilog before.
I wrote a simple code but I do not know how to generate the clock
signal.
this is my Code;
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 `include "cypress.v" //`#end` -- edit above this line, do not edit this line // Generated on 03/31/2017 at 15:12 // Component: ParalelToSerial module ParalelToSerial ( output Busy, output Clkout, output Dout, input Clkin, input [7:0] Data, input En ); //`#start body` -- edit after this line, do not edit this line reg busy; reg dout; reg clkout; reg [3:0]cnt_spi; reg clk_count; assign Busy = busy; assign Dout = dout; assign Clkout = clkout; always @ (negedge Clkin) begin if(En == 1'b1 && busy == 1'b0) begin clkout=1'b0; dout=Data[cnt_spi]; cnt_spi = cnt_spi + 1; end if(cnt_spi == 8) busy=1'b0; begin end end //`#end` -- edit above this line, do not edit this line endmodule
I will be glad if you help me. I'm just looking for a very simple
example of spi.