arve9066
Member level 2
Code:
process(rst, adcclock_80Mhz)
begin
if rst = '1' then
ADC_Timelog <= (others => '0');
ADC_Timecnt <= 0;
elsif adcclock_80Mhz'event and adcclock_80Mhz = '1' then
ADC_Timecnt <= ADC_Timecnt + 1;
time_ack <= '0';
if(ADC_Timecnt = 8192) then
ADC_Timelog <= ADC_Timelog + '1';
Timestamp <= "11" & "00" & cal1 & cal2 & ADC_Timelog;
time_ack <= '1';
ADC_Timecnt <= 0;
end if;
if time_ack='1' then
timelog1 <= timelog1+1;
timelog2 <= timelog2+1;
if timelog1 < 64 then
cal1 <= '1';
elsif timelog1 > 64 and timelog1 < 128 then
cal1 <= '0';
elsif timelog1 > 128 then
timelog1 <=0;
end if;
if timelog2 < 32 then
cal2 <='1';
elsif timelog2 > 32 and timelog2 < 64 then
cal2 <='0';
elsif timelog2 > 64 then
timelog2 <=0;
end if;
end if;
end if;
end process;
I am trying to generate two signals one that will be twice the frequency of the other from the signal time_ack, The code generates the two signals cal1 and cal2, but I see a phase difference between cal1 and cal2 and that is varying with time. Am I doing anything wrong generating these signals this way?