beginner_EDA
Full Member level 4
Hi,
I have 64 bit serial bus where I am suppose to send data serially and I tried as follows:
but the last 64 bit data(condition for else if (i == 2'b11)) is not coming.
What is wrong here? Is there any other way?
I have 64 bit serial bus where I am suppose to send data serially and I tried as follows:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 reg [15:0] gen_data_reg_7_6 = 16'd0; reg [15:0] gen_data_reg_5_4 = 16'd0; reg [15:0] gen_data_reg_3_2 = 16'd0; reg [15:0] gen_data_reg_1_0 = 16'd0; reg [1:0] i = 2'b00; always @(posedge aclk) begin i <= i + 1; if (i == 2'b00) begin gen_data_reg_1_0 <= 16'h2000; gen_data_reg_3_2 <= 16'hb505; gen_data_reg_5_4 <= 16'h0000; gen_data_reg_7_6 <= 16'h0201; end else if (i == 2'b01) begin gen_data_reg_1_0 <= 16'h8aa1; gen_data_reg_3_2 <= 16'hfea9; gen_data_reg_5_4 <= 16'h9df2; gen_data_reg_7_6 <= 16'h00e0; end else if (i == 2'b10) begin gen_data_reg_1_0 <= 16'hfc00; gen_data_reg_3_2 <= 16'h0494; gen_data_reg_5_4 <= 16'h0000; gen_data_reg_7_6 <= 16'h0016; end else if (i == 2'b11) begin gen_data_reg_1_0 <= 16'h0309; gen_data_reg_3_2 <= 16'h00e0; gen_data_reg_5_4 <= 16'hfc00; gen_data_reg_7_6 <= 16'hfc00; end end
but the last 64 bit data(condition for else if (i == 2'b11)) is not coming.
What is wrong here? Is there any other way?