eruisi
Member level 4
Hi, guru:
I wrote some RTL code, is there a quick way to tell me if there is any dead zone in the RTL w/o running any vector based Verilog simulation?
For example, if I accidentally tied clock input to a flop, I want to see some message like "The output of this flop will never toggle"
I know I can get this information from Primetime, but can we have a quick check at RTL level? If yes, what is the tool name?
Thanks
eruisi
I wrote some RTL code, is there a quick way to tell me if there is any dead zone in the RTL w/o running any vector based Verilog simulation?
For example, if I accidentally tied clock input to a flop, I want to see some message like "The output of this flop will never toggle"
I know I can get this information from Primetime, but can we have a quick check at RTL level? If yes, what is the tool name?
Thanks
eruisi