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Advanced Member level 4
Hi,
I have a code for extracting a ROM from a text file. I'v used it successfully in ISE 14.7 on a spartan6. synthesize and implementation was OK.
but now I want to use it on an artix project by vivado. unfortunately vivado can not synthesize the code currently .
the code is as below:
can any body help me plz.
the version of vivado : 2015.4
I have a code for extracting a ROM from a text file. I'v used it successfully in ISE 14.7 on a spartan6. synthesize and implementation was OK.
but now I want to use it on an artix project by vivado. unfortunately vivado can not synthesize the code currently .
the code is as below:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use std.textio.all;
entity My_Rom is
port( iClk :in std_logic;
iAddr :in std_logic_vector(9 downto 0);
oData :out std_logic_vector(15 downto 0)
);
end My_Rom;
architecture Behavioral of My_Rom is
type tRom is array (0 to 1023) of std_logic_vector(15 downto 0);
impure function RomExtc (RomFileName : in string) return tRom is
FILE RomFile : text is in RomFileName;
variable L : line;
variable RomData : tRom;
variable iData : integer;
variable qData : integer;
begin
report "Making Mapping_Rom:";
-- for ii in tRom'range loop
for ii in 0 to 1023 loop
readline (RomFile, L);
report "L: " & L.all;
iData:=0;
read (L, iData);
report "iData= "&integer'image(iData);
RomData(ii):=conv_std_logic_vector(iData,16);
end loop;
return RomData;
end function;
constant cRom : tRom := RomExtc("Rom.coe");
signal sAddr :std_logic_vector(9 downto 0):=(others=>'0');
signal sData :std_logic_vector(15 downto 0):=(others=>'0');
begin
process(iClk)
begin
if rising_edge(iCLk)then
sAddr <=iAddr;
sData <=cRom(conv_integer(unsigned(sAddr)));
end if;--Clk Rising
end process;
-- sData <=cRom(conv_integer(unsigned(sAddr)));
oData <=sData(15 downto 0);
end Behavioral;
can any body help me plz.
the version of vivado : 2015.4