design_engineer
Newbie level 6
Hello,
Due to design size constraints, I can only have a single fixed-point arithmetic unit (add/subtract/multiply/divide). I have a number of arithmetic operations I need to do in a pipeline. Based on the biggest original parameters for the multiplier which were UQ0.9 and UQ5.2 (and since there are also subtractions along the way), I chose a 16x16 bit signed fixed-point multiplier to do all operations. And I chose the multiplier's operands to be the generic size of 6:-9 to cover the biggest range and the smallest resolution of -9. I resize all parameters to this size before feeding to the multiplier.
However, now additional parameters have been introduced that are UQ7.0 (or SQ8.0) and have to go through the same multiplier.
Now I cannot accommodate both the SQ8.0 and the SQ1.9 parameters in the 16x16 sfixed multiplier. I understand that I cannot change the sizes of the operands of the multiplier on the fly correct? Because once I choose a size, it is fixed in hardware.
So what are my options here?
1. Increase the multiplier to 24x24 sfixed or even 32x32?
2. Change the multiplier operands to 8:-7 (losing resolution on the -9 parameter). What would be the effect of this?
3. Break up the SQ8.0 multiplication into two pieces that are Q6.0 each? Is this possible? (It would need an additional clock cycle)
4. One point is that a bunch of operations are unsigned only but I have to use signed arithmetic for everything because some intermediate terms become negative. This causes an extra bit to be used that affects my functionality. Is there any way to do both ufixed and sfixed operations in the same unit?
Any other solutions?
Thanks for any help.
Due to design size constraints, I can only have a single fixed-point arithmetic unit (add/subtract/multiply/divide). I have a number of arithmetic operations I need to do in a pipeline. Based on the biggest original parameters for the multiplier which were UQ0.9 and UQ5.2 (and since there are also subtractions along the way), I chose a 16x16 bit signed fixed-point multiplier to do all operations. And I chose the multiplier's operands to be the generic size of 6:-9 to cover the biggest range and the smallest resolution of -9. I resize all parameters to this size before feeding to the multiplier.
However, now additional parameters have been introduced that are UQ7.0 (or SQ8.0) and have to go through the same multiplier.
Now I cannot accommodate both the SQ8.0 and the SQ1.9 parameters in the 16x16 sfixed multiplier. I understand that I cannot change the sizes of the operands of the multiplier on the fly correct? Because once I choose a size, it is fixed in hardware.
So what are my options here?
1. Increase the multiplier to 24x24 sfixed or even 32x32?
2. Change the multiplier operands to 8:-7 (losing resolution on the -9 parameter). What would be the effect of this?
3. Break up the SQ8.0 multiplication into two pieces that are Q6.0 each? Is this possible? (It would need an additional clock cycle)
4. One point is that a bunch of operations are unsigned only but I have to use signed arithmetic for everything because some intermediate terms become negative. This causes an extra bit to be used that affects my functionality. Is there any way to do both ufixed and sfixed operations in the same unit?
Any other solutions?
Thanks for any help.
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