Sanketp20
Newbie level 5
Hi,
If I place low voltage fet in high voltage well, will that device be considered as high voltage as well ?
For example:
Let's consider 5 volt to be high volt in 28nm TSMC process. and 1.2V to be low volt.
Now if I place 1.2V pmos in 5V NWELL, will the voltage on nets connected to that pmos also considered 5V nets and should I enforce 5V metal spacing DRC rules on those nets ?
I appreciate your guidance.
Thanks
If I place low voltage fet in high voltage well, will that device be considered as high voltage as well ?
For example:
Let's consider 5 volt to be high volt in 28nm TSMC process. and 1.2V to be low volt.
Now if I place 1.2V pmos in 5V NWELL, will the voltage on nets connected to that pmos also considered 5V nets and should I enforce 5V metal spacing DRC rules on those nets ?
I appreciate your guidance.
Thanks