shaiko
Advanced Member level 5
Hello,
Already posted it on alteraforum.com but didn't get a lot of help - so I'll try again here.
I'm using a Cyclone V SOC FPGA.
Currently my design has 8 multipliers (which I coded in VHDL instead of instantiating).
The inputs to the multipliers are 12 and 16 bits wide.
According to this document:
https://www.altera.com/content/dam/...iterature/wp/wp-01159-arriav-cyclonev-dsp.pdf
I expected the tool to pack 2 multipliers into a single DSP block - so that for 8 multipliers only 4 DSP blocks shall be consumed.
Unfortunately - the compilation report shows that 8 DSP blocks are consumed (one per each multiplier).
I tried to change the synthesis behavior to area driven - but nothing changed.
Any idea what can cause such behavior ?
Already posted it on alteraforum.com but didn't get a lot of help - so I'll try again here.
I'm using a Cyclone V SOC FPGA.
Currently my design has 8 multipliers (which I coded in VHDL instead of instantiating).
The inputs to the multipliers are 12 and 16 bits wide.
According to this document:
https://www.altera.com/content/dam/...iterature/wp/wp-01159-arriav-cyclonev-dsp.pdf
I expected the tool to pack 2 multipliers into a single DSP block - so that for 8 multipliers only 4 DSP blocks shall be consumed.
Unfortunately - the compilation report shows that 8 DSP blocks are consumed (one per each multiplier).
I tried to change the synthesis behavior to area driven - but nothing changed.
Any idea what can cause such behavior ?
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