wtr
Full Member level 5
Hello all,
I'm looking at some legacy code. The guy has done the following
The use of a natural is used to allow the case statement to have a range.
I know slv ranges' wasn't allowed in the 93 vhdl.
nowadays could I do
Or do I need some fancy subtype range?
At this moment of time I haven't got access to a tool licenses check if this synthesis
Regards,
Wes
I'm looking at some legacy code. The guy has done the following
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PADDR : in std_logic_vector(31 downto 0); ------------------------------------------------------------ signal PADDR_N : natural range 0 to 1048575; -- 2^20 = [19:0] ------------------------------------------------------------ -- APB Bus PADDR_N <= conv_integer(PADDR(19 downto 0)); ------------------------------------------------------------ if PSEL = '1' and PWRITE = '0' then case PADDR_N is -- MRI-0 (Base: 0x0000_0000) when 16#00000# => PRDATA <= FPAD_SLV(32, ARM_WR_MRI0_DARK_START_S); --- more options when 16#B8000# to 16#B9FFC# => PRDATA <= ARM_RD_FDDR_RDATA; -- 8KB Address Space
The use of a natural is used to allow the case statement to have a range.
I know slv ranges' wasn't allowed in the 93 vhdl.
nowadays could I do
Code VHDL - [expand] 1 when x"B8000" to x"B9FFC" => PRDATA <= ARM_RD_FDDR_RDATA; -- 8KB Address Space
Or do I need some fancy subtype range?
At this moment of time I haven't got access to a tool licenses check if this synthesis
Regards,
Wes