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Asserion in Systemverilog with Questasim

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shahsanket24

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Hello all...

I have written simple assertion in SV... Can anyone tell me how to execute the same in Questa...? In the sense exact command or steps to be followed to exexcute it...?

Thanks to all...
 

shahsanket24 said:
Hello all...

I have written simple assertion in SV... Can anyone tell me how to execute the same in Questa...? In the sense exact command or steps to be followed to exexcute it...?

Thanks to all...
Click to expand...

Eg
Design file -example.sv
top module -top

Code: 
vlog example.sv 
vopt +acc=a top -o dbgver
vsim -assertdebug dbgver
atv log -enable /top

run 500

view assertion
 
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    shahsanket24

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Thank u Very much blooz....
But i want to know the significance of the command- atv log -enable /top..
Because even if i am excluding this i am getting assertion error message if i am intentionally inserting an error to my code....
 

When complex assertions are triggered, it can be challenging to determine the cause of the failure . Assertions can be logged to the Wave window where activation, success, and failure states are easily identified. Since assertions can have multiple threads in concurrent evaluation,Questasim includes an innovative Assertion Thread Viewer, which graphically shows the complete evaluation of an activated assertion.

---------- Post added at 10:44 ---------- Previous post was at 10:42 ----------
shahsanket24 said:
Thank u Very much blooz....
But i want to know the significance of the command- atv log -enable /top..
Because even if i am excluding this i am getting assertion error message if i am intentionally inserting an error to my code....
Click to expand...

atv log -enable /top.. Here top is supposed to be the name of top module ,replace it with your top module .
 

Screenshot.png

By executing i am getting error so can u plz help me in rectifing it...?
 

Screenshot-1.png

I have use design module name only eventhough it is showing above error.
 

shahsanket24 said:
View attachment 65621

I have use design module name only eventhough it is showing above error.
Click to expand...
I think you did n't use the
Use the +acc=a argument with the vopt command
or -voptargs=+acc=a argument with
the vsim command


atv log
This command enables or disables assertion thread viewing (ATV) for the specified assertion.
Multiple assertions may be specified by their pathnames.

Prerequisites
Use the +acc=a argument with the vopt command or -voptargs=+acc=a argument with
the vsim command


•Use the -assertdebug argument with the vsim command
 
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