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how to reduce parasitic resistance on the layout

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allennlowaton

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Hello EDA fellows,

The graph below shows the post simulation using the R+C+CC and C+CC extractions.
The problem can be traceable to the parasitic resistance.
The expected result is the same as that of the C+CC.
My concern now is how to reduce the parasitic resistance in the layout.

 

No. The parasitic resistance being obtained from the layout.
 

I have no idea on specifics of LED and associated Layout.
In general :
1. Widen the wires if possible [not violating DRC of course].
2. In case there are multiple metal layers - between layers in case you have VIA - increase the number of Via-counts in parallel, that will reduce parasitic resistance.
 
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