soloktanjung
Full Member level 6
Hello,
My design has 2 different and independent clocks. So I constraint it using:
After loading the constraints, I got this warning:
My question is: should I care about the warning? Is it important for timing accuracy?
Thank you.
Hairo
My design has 2 different and independent clocks. So I constraint it using:
Code:
set_clock_groups -async -group clock1 -group clock2
set_ideal_network [get_ports clock1]
set_ideal_network [get_ports clock2]
After loading the constraints, I got this warning:
Warning: Clock port 'clock1' is assigned input delay relative to clock 'clock2'. (TIM-111)
My question is: should I care about the warning? Is it important for timing accuracy?
Thank you.
Hairo