Help:Very low power CMOS SAR ADC with INV as the comparator

It use INVETER as comparator in B.bechen' paper: A 10 bit very low-power CMOS SAR-ADC for capacitive micro-mechanical pressure measurement in implants, the scheme just like the pic;
Could Anyone please explain more detail about this circuit, or give more document about this ? Thanks

There's another circuit in a 8 Bit SAR ADC, the Comparator is like this pic

From analog viewpoint an inverter can be assumed as single-ended comparator with fixed and pure defined threshold voltage, strongly depending on PVT(i.e. Vdd/2+Vos, where Vos(PVT) ~ +/-30%Vdd). To reduce this dependence an offset periodical correction method is used. That is devision a comparator desision interval into 2 parts: during first half an offset is stored on capacitor by closing analog switch between inverter input and output, during second half switch is opened and signal sign decision is produced. In SAR ADC all capacitor matrix serves for offset storing of first inverter/amplifier stage. To increase comparator accuracy an offset voltage of second inverter/amplifier stage can be done by inserting additional storage capacitor between stages and switch around second stage.

Thanks milersia
The 2nd pic follows your explain if Vin connect to Cap matrix. Then Cap maxtrix and the Cap between the two inverter act as Vos cancellation cell, and Inv1 & Inv2 are two amplifier, isn't it?

right, Inv1 & Inv2 are two amplifiers with offset correction