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how to measure an area of a transistor

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aglonen

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how to calculate an area of a transistor in 0.35um technology in virtuoso layout. The width of my transistor in schematic is 20um and length is 0.35um. Do i expect to get same dimensions in layout, they look different?? any help??
 

The area is simply the width x length, although I suspect that isn't what you're asking. Select the transistor and press q, this will tell you the dimensions etc (and allow you to modify them), of your transistor, check how many fingers there are for the device - this could throw you off. If you still are unsure use the ruler function to measure it, I can't remember the short-cut just now as I've not used cadence for a while (k maybe)
 

The total area is not just W*L. If we are talking about the poly gate area, sometimes default value for poly extension is added in layout, which is not present in schematic. Also if we are talking about whole transistor area, then gate to contact spacing and LOD comes into play, which may not always be captured in schematic, which adds diffusion area to poly area.
If you are interested in estimating layout area for a particular schematic. Dump all cells in layout blindly. Find the area. Multiply it by factor between 1.2 - 2 depending on packing density to be achieved. It will be 1.2 for capacitor bank layout and 2 when a lot of routing is involved. Hope this helped.
 
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