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Regarding the Xilinx Jtag programmer connector details

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I have all the cables. parallel and USB. Both USB (Platform cable USB - dlc9g and Platform cable USB II-dlc10)
they all work with the CPLD and FPGA. chip scope did not try

---------- Post added at 16:46 ---------- Previous post was at 16:44 ----------

I have already said that regardless of the type of cable JTAG interface is the same. 14 pin connectors are identical.
 
Hi,

Can u have the dimension for the Jtag connector used in the target board for hardware design


thanks,
V. Prakash
 

Molex 87832-1420

---------- Post added at 13:39 ---------- Previous post was at 13:37 ----------

2.0mm 7x2 shrouded header
 

yes.
dimension is correct
 

Hi,

To which pin of the CPLD, I have to connect this HALT Pin of JTAG?
Please do let me know.

Thanks,
V. Prakash
 

prakashvenugopal said:
To which pin of the CPLD, I have to connect this HALT Pin of JTAG?
Click to expand...

CPLD?

Is this the Coolrunner II design?

If so, I do not believe the Coolrunner II supports that particular line, so leave it NC.



As a matter of fact, you do not even need the shrouded header connector, just use a single row header strip which can be attached to by flying leads.

BigDog
 
Hi,

I am planning to work with FPGA also: in case of FPGA, to which pin of FPGA, i have to connect that HALT pin of Jtag?

For CPLD:
Halt pin -- Open
Pgnd -- ? (what was this pseudo gnd? will have to connect to the supply gnd? )
gnd -- ? (will this is the supply gnd?)



For FPGA:
Halt pin -- (to which pin of FPGA, i have to connect this HALT of Jtag?)
Pgnd -- ? (what was this pseudo gnd? will have to connect to the supply gnd? )
gnd -- ? (will this is the supply gnd?)

Please let me know so that it will be useful for my PCB design

thanks,
V. Prakash
 

I will kill you guide a boat ("C" shown in the Russian film)

you little problems? more later jtag is the more it is functional. Now I begin to use foul language. If you need some tips ---- Bring them out.
 

Hi,

If you know and interested to answer. You answer for this?

For CPLD:
Halt pin -- Open
Pgnd -- ? (what was this pseudo gnd? will have to connect to the supply gnd? )
gnd -- ? (will this is the supply gnd?)


For FPGA:
Halt pin -- (to which pin of FPGA, i have to connect this HALT of Jtag?)
Pgnd -- ? (what was this pseudo gnd? will have to connect to the supply gnd? )
gnd -- ? (will this is the supply gnd?)

Please let me know so that it will be useful for my PCB Design

---------- Post added at 09:42 ---------- Previous post was at 09:18 ----------

Hi treqer,

I am not a Ph.D in FPGA and CPLD's. I am just an L.K.G in it. I have to clear my all doubts before starting my Hardware design. I am trusting you people to clarify my doubts in design. Please Co-operate.

Thanks,
V. Prakash
 

Why reinvent the wheel? BIG DOG made ​​reference to the scheme. A lot of EVMs schemes can be found at Avnet. Do as humans do.
 

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