[SOLVED] PLL and FPGA operating frequency relation ?

Would the presence of PLL affect the operating frequency of an FPGA ? When operating frequency of the FPGA can be maximum (with PLL or without PLL) ?

What is the (general) supported input frequency range of any PLL present in an FPGA (Xilinx or Altera or Actel) ?

Please note this question is generic one. Not specific to any FPGA device.

FPGA specific answers are also welcome.

Thanks
Vasanth

I am currently using a virtex-5 with a 500MHz differential clock that is DCM'ed down to 250MHz for the logic, and 125MHz for the powerpc/bus/etc. I believe that xilinx virtex-5 powerpcs can run up to 250MHz (good luck meeting timing though) and the fabric can run up to 500MHz.

well,

The operating speed/frequency of the FPGA is determined by the type of blocks used in it, ie, the LUTs, LEs/LCs, etc. For a particular FPGA family, the vendor would have provided the max frequency after testing the FPGA with various clocks. The other factor that contributes to the speed of an FPGA is the IO speed, type. The PLLs/DCMs in the FPGA are provided so that designers can generate the clocks they need by using a single clock input at the GCLK pin and generating required clocks via PLLs/DCMs.

The presence or absence of a PLL/DCM does not increase/decrease the operating frequency of the FPGA. The more number of PLLs/DCMs in the FPGA, the better, coz we can use them to generate as many clock frequencies that we require in the design.

Thanks vlsi_whiz. Your reply answers my question very well.

The DCM utilizes fully digital delay lines allowing robust high-precision control of clock phase and frequency. . what does this mean ??

It means they have a digital delay line with multiple taps. And it can be used for the control of clock phase and frequency. You can read the Clocking Resources section for the fpga of your choice. It's got plenty of information on this.