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HOW it is done in cadence.

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muffassir

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Hi all,

I am newbie in Design using Cadence please help me out .I have this screenshot(attached) of the manual that i am working out on.

See the image .In image u can see markings as 1 and 2.
As it is known that the bulk/substrate is connected to ground in nmos so we connect substrate and source directly together and then to ground.
But see in Mark 1 the Substrates of both the nmos are connected to eachother by wire and vss is written above it.

Is it(Mark 1) is correct?
If Yes then how to do it using cadence?(I mean how to write that vss )



Thanks in advance
 

When In Schematic Editor, press L or click on Create --> Wire Name. A pop up window will appear where you can enter the name of the net. Enter the name of the net and press enter or click on Hide, the net name with a small dot will appear above the mouse cursor. Place the dot on top of the net you want to name.
Thats it, you're finished!
 
Hi muffassir

As u shown in screenshot, it is nothing but connecting substrates of both transistors to VSS, while drawing layouts.
In schematic , it is represented as both are connected to VSS.

Thank You
Regards
T.Prasad
 

Do any one have allegro cadence evaluation version.I am searching for it to learn PCB designing
 

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