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Cadence Virtuso: How to model current limiter

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Hi All,

May I know if there is a way to model a current limiter in cadence. I need to desing an amplifier with a current of 100uA in the second stage. I want to model this to see how the transient responce is when driving the capacitive load.

Thanks a lot in advance!!
M.
 

Why not directly use current mirror OTA with 100uA output?
 

in case of using Cadence/Spectre simulator an "Voltage Controlled Voltage Source" instance (i.e. "vccs") can be used simply with the defined minumum and maximum output current limits.

in case of behavioral (e.g. VerilogA) module description a construction "if ... else if ..." should help:
...
if (Iout > Ilim) begin
Iout = Ilim;
end
else if (Iout < -Ilim) begin
Iout = -Ilim;
end
...
 
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