How to connect body of a NMOS,when I am applying a voltage source to body terminal

Hi all,
I am using umc 0.18um RF/Mixedmode CMOS technology in my project.I have used three terminal inductor,capacitor,resistor and four terminal NMOS in my design.after designing the schematic I have used the gen from source option to create the layout of different component.after that I have connected all the components.but I am getting problem in connecting the body terminal(showing pin mismatch error in LVS).As I have applied a voltage source to the body terminal in schematic so in layout I have connected metal1 layer with the body and connected a pin with that layer with same name as in layout.In layout view of the NMOS I have observed it has Diff layer sorrounding the NMOS, over the layer Diff there is cont_p layer,metal1 layer and p+ layer thats why I have used metal1 layer to connet body. Please correct me if somewhere I am wrong and suggest me how I will solve the problem. I really need help in this regard if anyone working with the RF component of umc or know about it.

the NMOS body is the global substrate common to all other devices, usually connected to 0V, if you want to connect it to a different voltage you need to isolate it with a deep n-well to create an isolated p-well around the NFETs

dgnani said:

the NMOS body is the global substrate common to all other devices, usually connected to 0V, if you want to connect it to a different voltage you need to isolate it with a deep n-well to create an isolated p-well around the NFETs

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Thanks for the reply.Actually I am not creating the lay out of the mos by putting layer over layer, what I am doing is I am using the option gen from source in lay out editor by which I am getting the lay out view of the NMOS transistors and all other components,which I am just connecting together.I can see there is a Pdiff layer arround all the NMOS ,does it mean that all these Pdiff layers are connected??and over the Pdiff layer a metal1_Pdiff contact is there.one more thing are you advising me to use twin well process??please correct me if somewhere I am wrong as I am a novice to this field.and I am really thankful to you for giving your time to this post.

even if the layout is generated automatically by layout XL if you chose the wrong devices in the schematic you won't get a working design. UMC18MM/RF uses a p-substrate wafer so all NFET bodies are connected together by the resistive substrate (this is usually called a soft connection). You cannot use different voltages on the bodies unless the NFETs using those voltages are isolated from the global substrate using a deep n-well (you need at least one deep n-well for each separate voltage group). The schematic usually requires using different NFET devices in this case but I do not recall what the case is for UMC18.
Twin well process and the availability of deep nwell are different things, w/o going into this UMC18 has a deep n-well option available.