How to simulate an Opamp for input common mode range (ICMR)

Hello all,

Today I have simulated an Two-stage opamp to find out its ICMR.
To find out ICMR i gave dc input @ VIN+, & VIN- is connected to VOUT. And plotted VOUT after DC simulation.
As nmos differential pair is used at input, i was expecting the VOUT to be linear from V1 to VDD ( where V1 > GND ). But surprisingly, VOUT vs VIN+ plot shown the linear result. means VOUT is following VIN+ linearly (like rail-to-rail opamps)!!!!!

so when i checked manually, i found some transistors are not in saturation region!!!!

some books say "ICMR is the range over which all transistors will remain in saturation".

and Allen's book says "ICMR is the range over which amplifier amplifies the diff signal with same gain".

as it obvious that gain will reduce if all transistors are not in saturation.

So does it mean to find out the ICMR (DC characteristic of opamp) i need to do AC simulation?
And if i do the DC simulation i need to check all transistors operating region manually?

Or is there any other method to find out ICMR?

PLZ HELP...

I would consider the first definition as the correct one.
However, this definition is also not verifiable on actual silicon.
Hence, the need for Allen's definition.

checkmate said:

I would consider the first definition as the correct one.
However, this definition is also not verifiable on actual silicon.
Hence, the need for Allen's definition.

Click to expand...

First definition means DC analysis!!!
For two-stage op-amp (nearly 8 mos devices) its fine, but what if its multistage opamp ?
this dc simulation method doesn't look practical. Isn't it?

I say that common mode range is the range over which your
design meets spec. All of them. Unless you and your customer
agree otherwise.

It's much easier if you attach your VCC and VEE (VDD and VSS)
supplies to a third, VCM supply instead of ground. Then you
can sweep or step that and not have the signals moving away
from reference ground. You will see dedicated op amp ATE
product test programs work this way, so that they can make
best use of the range/resolution tradeoff inherent in pin cards.

For DC you'd expect the thing to meet Vio, AVOL, IIB/IIO.
For AC, you want to see the same GBW product and no
big change in phase. And be sure to run a transient sim of
some sort especially if it's got bipolars in the first stage to
see if there's a saturation hangup near one rail or the other,
or maybe the tail source is getting choked but maybe not
visible in small signal / DC.

Hi,

You just only measure drain current of main couple transistors in OPAMP to get active region point ( see attached files) . It will make all transistors remain in saturation. Doing AC simulation is not necessary.

Hi,
The OP must have some SPECs that one concerns mostly.
I 'd like to define the ICMR, in which all the other SPECs meet my requirement.

Hello,

There is one more or less practical method for ICMR simulation I've ever seen.
It requires to perform AC sweep analysis. Sweep is over ICM voltage at lowest
frequency corresponding to DC gain. After AC sweep diff. gain is analyzed as function of the ICM voltage. Points where the gain drops by 3dB with respect to flat band value can be considered as edges of ICMR.

Regards