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how to design the size of buffer stage in PLL VCO?

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turtlewang

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hello everyone,

I am designing a buffer stage used in PLL ring oscillator. the schematic is shown in the following picture.

I want to know how to design the size of transistors shown in the schematic to gain low noise.

Is there any materials on this topic? buffer_VCO1.jpg
 

I guess you are referring to phase noise here. I cannot give you a step by step procedure but you will have to focus on matching both w/i each stage and among stages. Having the control voltage modulating the current load does not seem as good as modulating the tail current (since the first method relies on matching of separate PMOSs). Other useful points for matching are to use:
- large area diff pair (low offset)
- current sources in strong inversion
- ratioed PMOSs to define positive feedback switching point
- minimize PMOSs Vt mismatch
- verify impact of thermal and 1/f noise using transient noise with MC mismatch sim
- verify impact of PSRR on both rails
- use layout matching tricks if is to be actually implemented

Knowing what process you are using would help to know what to focus on. I am sure you already know most of this but I hope some of it will help
 
dgnani said:
I guess you are referring to phase noise here. I cannot give you a step by step procedure but you will have to focus on matching both w/i each stage and among stages. Having the control voltage modulating the current load does not seem as good as modulating the tail current (since the first method relies on matching of separate PMOSs). Other useful points for matching are to use:
- large area diff pair (low offset)
- current sources in strong inversion
- ratioed PMOSs to define positive feedback switching point
- minimize PMOSs Vt mismatch
- verify impact of thermal and 1/f noise using transient noise with MC mismatch sim
- verify impact of PSRR on both rails
- use layout matching tricks if is to be actually implemented

Knowing what process you are using would help to know what to focus on. I am sure you already know most of this but I hope some of it will help
Click to expand...

Thanks dgnani,

1 Actually, here I want to get the lowest phase noise;
2 what is the meaning of "w/i"?
3 I use TSMC 0.18um to implement this ring oscillator;
4 I want to know the relationship between VCO gain and tail current if this ring oscillator has four stages;

thanks very much!
 

Can anybody give me some advices?

For example,

1 how to get the tail current according to the phase noise spec?

2 since the circuit works in large signal condition, how to calculate the size of the differential pair and active load? eg. the aspect ratio of the differential pair and active load?

3 I guess the current have mean value and its maximum value, do I use the mean value to calculate the aspect ratio?

Any comments are welcomd!

Thanks
 

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