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Why latch is created in this circuit

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otis

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Hi I saw this circuit some where in the internet. It says Latch is created.. But why?

always @(a, b) begin
temp = a – b;
if ((temp < 8’b0) && abs) // latch!
out = -temp;
else out = temp;
end

Thanks!
 

otis said:
Hi I saw this circuit some where in the internet. It says Latch is created.. But why?

always @(a, b) begin
temp = a – b;
if ((temp < 8’b0) && abs) // latch!
out = -temp;
else out = temp;
end

Thanks!
Click to expand...

Hi, You'd better synthesis this small circuit by any synthesis tool, such as DC, XST or synplify. Then you will get the answer.
Just try it.
 
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    otis

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Hi Ortis,

"always" is a construct in verilog which translates to either a latch or flop based on the sensitivity list...so if you use keyword such as pos/negedge instead if signals in the sensitivity list it will be translated to flop or else a latch...and as yang suggested please synthesize the code in a tool for better understanding

useful???
 
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    otis

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@phoenixpavan
Thanks for the explanation. If I have access the synthesis tool I would not ask here :)
Most people recommend to synthesis but is bit complicated to get access to synthesis tool they ask here.

Thanks for your time !
 

otis said:
@phoenixpavan
Thanks for the explanation. If I have access the synthesis tool I would not ask here :)
Most people recommend to synthesis but is bit complicated to get access to synthesis tool they ask here.

Thanks for your time !
Click to expand...

Hi, otis:
"always" statement will synthesis to combination logic, Latch(with combination logic) or DFF (with combination logic).
You must know how to synthesis to purely combination logic and DFF(with combination logic).
How it will synthesis to Latch(with combination logic)?? Do you get the idea. You can search this in the google for detail.

For the circuit you print out, I don't think it will be synthesised to a Latch(with combination logic) but it just has another problem:
The sensitive list incomplete problem (signal abs doesn't include in the sensitive list). Then you must wonder will this causing problem?? You'd better also search on google.

For enginerring, try it is a good way, I think,

Thanks,
 

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