Problem in UMC_18_CMOS_RNPPO_MM

can anyone help me in using the UMC_18_CMOS_RNPPO_MM resistor in schematic. I have connected the third terminal to Vdd, but still the device is not working. I am facing a similar problem with UMC_18_CMOS+RNPPO_MM. How to use these things?

I don't have your exact PDK (I used the CIS version) and the RNPPO_MM device works fine. Can you give us details e.g. resulting netlist, simulator used, etc

I am attaching few images of the simple circuit & also the output waveform along with the netlist:


// Generated for: spectre
// Generated on: Mar 15 16:13:09 2011
// Design library name: Deepon
// Design cell name: resistance_test2
// Design view name: schematic
simulator lang=spectre
global 0
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/core_rf_v2d4.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/io_rf_v2d3.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/l_slcr20k_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/mimcapm_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_MIMCAP_V101.lib.scs" section=mimcaps_typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG18BPW_V123.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG18_V124.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG33BPW_V123.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG33_V114.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_RES_V133.lib.scs" section=res_typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_ZVT18_V121.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_ZVT33_V113.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_LVT33_V113.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_LVT18_V113.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/pad_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/rnhr_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/rnnpo_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/rnppo_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/vardiop_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/varmis_18_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_BJT_V112.mdl.scs"
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_DIODE_V113.mdl.scs"

// Library name: Deepon
// Cell name: resistance_test2
// View name: schematic
V0 (net1 0) vsource dc=5
R1 (Out 0 0) resistor
R0 (net1 Out 0) resistor
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save R0:1 R1:1
saveOptions options save=allpub


The circuit:


The output waveform:

HI Deepon

I do not know Spectre that well, still I can tell you that the netlist is messed up.
The netlister did not add the correct model type, nor its w and l (assuming these properties are common to my RNPPO in UMC18 CIS PDK)

So you have a netlister problem which can come from
a missing techfile: did you attach the techlibrary to your design library?
OR a broken CDF (you need to look at it with Tools>CDF>Edit

Other points:
your schematic shows RNNPO instead of RPPO resistors

yes it is showing RNNPO, the same problem exists even if I use RNPPO...
I am cheking onto the techfile problem..

---------- Post added at 15:24 ---------- Previous post was at 15:14 ----------

I changed the width & length of the MOSFET, now check the new netlist, however, still we have no output...
I told you, every other resistors are working properly. Particularly RNNPO_MM & RNPPO_MM are not working. I am using analog design environment.


The netlist:

// Generated for: spectre
// Generated on: Mar 16 15:15:28 2011
// Design library name: Deepon
// Design cell name: resistance_test2
// Design view name: schematic
simulator lang=spectre
global 0
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/core_rf_v2d4.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/io_rf_v2d3.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/l_slcr20k_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/mimcapm_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_MIMCAP_V101.lib.scs" section=mimcaps_typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG18BPW_V123.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG18_V124.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG33BPW_V123.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_REG33_V114.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_RES_V133.lib.scs" section=res_typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_ZVT18_V121.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_ZVT33_V113.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_LVT33_V113.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_LVT18_V113.lib.scs" section=tt
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/pad_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/rnhr_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/rnnpo_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/rnppo_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/vardiop_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/varmis_18_rf_v2d3.lib.scs" section=typ
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_BJT_V112.mdl.scs"
include "/cad/Cadence/UMC018/UMC_MS/DESIGNKIT/UMC_18_CMOS//../Models/Spectre/MM180_DIODE_V113.mdl.scs"

// Library name: Deepon
// Cell name: resistance_test2
// View name: schematic
V0 (net1 0) vsource dc=5
R1 (Out 0 0) resistor wr=1.5u lr=2.5u
R0 (net1 Out 0) resistor wr=1.5u lr=2.5u
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=100n write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save R1:1
saveOptions options save=allpub