ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 compone

ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 compone

Hello

I am using ISE 12.3 to simulate my design,the device family is virtex 6.I got this error while mapping my design - ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 component.

When i looked for it in Xilinx i got a link - **broken link removed** where this error and its solution is given.

I am using Linux(Fedora - 11) as my platform.As mentioned in the solution i tried to set the environment using setenv XIL_MAP_OLD_SAVE 1 command in the root command prompt.After that i used echo $XIL_MAP_OLD_SAVE to check the result.The env was set.I restarted ise, but still when i am trying to map my design i am getting the same error.

Is there any other way to get rid of this error.

Any advice will be of great help.



Thanks in advance.

Re: ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 com

upal said:

I am using ISE 12.3 to simulate my design,the device family is virtex 6.I got this error while mapping my design - ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 component.

Click to expand...

Hey, I know that error! ;-)

To prevent me guessing at your design, could you post the module that instantiates the CARRY4? Preferably the entire module, not just the CARRY4 instantiation itself.

Re: ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 com

Its an 8bit adder made by using Xilinx Primitives.
-- code for addition of two 8 bit numbers using carry chain primiitive and flip flop
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;

entity ccadder_ff is
port (
Cout: out std_logic:='0';
Sum : out std_logic_vector(7 downto 0):="00000000";
Xi : in std_ulogic_vector(7 downto 0);
Yi : in std_ulogic_vector(7 downto 0);
Cinp,clk: in std_ulogic
);
end entity;
------------------------------------------------------------------
architecture structure of ccadder_ff is
signal c : std_ulogic_vector(8 downto 1);
signal i : std_ulogic_vector(7 downto 0);
signal a : std_logic_vector( 7 downto 0);
signal d : std_logic_vector(8 downto 1);
signal e : std_logic_vector(7 downto 0);

signal xif,yif :std_ulogic_vector(7 downto 0) := "00000000";
signal x,y : std_ulogic_vector(7 downto 0):="00000000";
signal s,sf : std_logic_vector(7 downto 0):="00000000";
signal co,cof : std_logic:='0';
signal ci : std_ulogic;
signal cif: std_ulogic:='0';


begin
-------------------------------------------------------------
dff1rocess(clk,Xi)
begin
if(clk'event and clk='1') then
xif<=Xi;
end if;
end process dff1;
dff2rocess(clk,Yi)
begin
if(clk'event and clk='1') then
yif<=Yi;
end if;
end process dff2;
dff3rocess(clk,cinp)
begin
if(clk'event and clk='1') then
cif<=cinp;
end if;
end process dff3;
dff4rocess(clk,cof)
begin
if(clk'event and clk='1') then
Cout<=cof;
end if;
end process dff4;
dff5rocess(clk,sf)
begin
if(clk'event and clk='1') then
Sum<=sf;
end if;
end process dff5;
-------------------------------------------------------------------------------
F1 : FD
generic map(
INIT => '0'
)
port map(x(0),clk,xif(0));
F2 : FD
generic map(
INIT => '0'
)
port map(y(0),clk,yif(0));

L1 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(1),i(0),x(0),y(0),'0','0','0','1');
-------------------------------------------------------------
F3 : FD
generic map(
INIT => '0'
)
port map(x(1),clk,xif(1));
F4 : FD
generic map(
INIT => '0'
)
port map(y(1),clk,yif(1));

L2 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(2),i(1),x(1),y(1),'0','0','0','1');
--------------------------------------------------
F5 : FD
generic map(
INIT => '0'
)
port map(x(2),clk,xif(2));
F6 : FD
generic map(
INIT => '0'
)
port map(y(2),clk,yif(2));

L3 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(3),i(2),x(2),y(2),'0','0','0','1');
---------------------------------------------------
F7 : FD
generic map(
INIT => '0'
)
port map(x(3),clk,xif(3));
F8 : FD
generic map(
INIT => '0'
)
port map(y(3),clk,yif(3));

L4 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(4),i(3),x(3),y(3),'0','0','0','1');
--------------------------------------------------------------------------------------------------------------------------------
d<=To_stdlogicvector(c);
e<=To_stdlogicvector(i);

F_1 : FD
generic map(
INIT => '0'
)
port map(ci,clk,cif);
P1 : CARRY4
port map ( CO=>a(3 downto 0),O=>s(3 downto 0),CI=>ci,CYINIT=>'0',DI=>d(4 downto 1),S=>e(3 downto 0));
----------------------------------------------------------------------------------------------------------------------------------
F9 : FD
generic map(
INIT => '0'
)
port map(x(4),clk,xif(4));
F10 : FD
generic map(
INIT => '0'
)
port map(y(4),clk,yif(4));

L5 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(5),i(4),x(4),y(4),'0','0','0','1');
---------------------------------------------------
F11 : FD
generic map(
INIT => '0'
)
port map(x(5),clk,xif(5));
F12 : FD
generic map(
INIT => '0'
)
port map(y(5),clk,yif(5));

L6 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(6),i(5),x(5),y(5),'0','0','0','1');
---------------------------------------------------
F13 : FD
generic map(
INIT => '0'
)
port map(x(6),clk,xif(6));
F14 : FD
generic map(
INIT => '0'
)
port map(y(6),clk,yif(6));

L7 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(7),i(6),x(6),y(6),'0','0','0','1');
----------------------------------------------
F15 : FD
generic map(
INIT => '0'
)
port map(x(7),clk,xif(7));
F16 : FD
generic map(
INIT => '0'
)
port map(y(7),clk,yif(7));
L8 : LUT6_2
generic map(
INIT => X"6666666688888888"
)
port map(c(8),i(7),x(7),y(7),'0','0','0','1');
----------------------------------------------
P2 : CARRY4
port map ( CO=>a(7 downto 4),O=>s(7 downto 4),CI=>a(3),CYINIT=>'0',DI=>d(8 downto 5),S=>e(7 downto 4));
----------------------------------------------------------------------------------------------------------------------------
co<=a(7);
F_2 : FD
generic map(
INIT => '0'
)
port map(cof,clk,co);
-----------------------------------------------------------------------------------------------------------------------------
F_3 : FD
generic map(
INIT => '0'
)
port map(sf(0),clk,s(0));

F_4 : FD
generic map(
INIT => '0'
)
port map(sf(1),clk,s(1));

F_5 : FD
generic map(
INIT => '0'
)
port map(sf(2),clk,s(2));

F_6 : FD
generic map(
INIT => '0'
)
port map(sf(3),clk,s(3));

F_7 : FD
generic map(
INIT => '0'
)
port map(sf(4),clk,s(4));

F_8 : FD
generic map(
INIT => '0'
)
port map(sf(5),clk,s(5));

F_9 : FD
generic map(
INIT => '0'
)
port map(sf(6),clk,s(6));

F_10 : FD
generic map(
INIT => '0'
)
port map(sf(7),clk,s(7));

end structure;
---------------------------------------------

Thanks in advance.

Re: ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 com

Aha! As I suspected. I did the very same thing not too long ago.

Actually the error message describes precisely what's wrong....

ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 component.

Click to expand...

You are trying to connect "ci" to the carry in of the CARRY4 chain. Only the carry out another CARRY4 chain (the one in the previous slice) can be routed to the carry in of a CARRY4.

To feed the carry at the start of the chain, you can use the CYINIT port. So in your case that would be something like:


(swapped the values for CI and CYINIT)

Hope that helps.

PS: I normally work in verilog, so I am not 100% certain if the above "CI" portmapping is correct. If it tells you that you cannot set CI and CYINIT at the same time (I got that error in verilog), then you should use an "empty port" for CI (however you do that in vhdl).

Re: ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 com

Thanks a lot.

Re: ERROR:LIT:407 - CI of CARRY4 symbol "<inst>" must be driven by another CARRY4 com

mrflibble said:

Aha! As I suspected. I did the very same thing not too long ago.

Actually the error message describes precisely what's wrong....

You are trying to connect "ci" to the carry in of the CARRY4 chain. Only the carry out another CARRY4 chain (the one in the previous slice) can be routed to the carry in of a CARRY4.

To feed the carry at the start of the chain, you can use the CYINIT port.

Click to expand...

Thank you! Got bit by this just today and found your solution very helpful. Moved the incoming signal to the CYINIT port and it worked beautifully.

..dane